A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology