The optimally-sampled galaxy-wide stellar initial mass function - Observational tests and the publicly available GalIMF code

Here we present a full description of the integrated galaxy-wide initial mass function (IGIMF) theory in terms of the optimal sampling and compare it with available observations. Optimal sampling is the method we use to discretize the IMF into stellar masses deterministically. Evidence has been indicating that nature may be closer to deterministic sampling as observations suggest a smaller scatter of various relevant observables than random sampling would give, which may result from a high level of self-regulation during the star formation process. The variation of the IGIMFs under various assumptions are documented. The results of the IGIMF theory are consistent with the empirical relation between the total mass of a star cluster and the mass of its most massive star, and the empirical relation between a galaxy's star formation rate (SFR) and the mass of its most massive cluster. Particularly, we note a natural agreement with the empirical relation between the IMF's power-law index and a galaxy's SFR. The IGIMF also results in a relation between the galaxy's SFR and the mass of its most massive star such that, if there were no binaries, galaxies with SFR $<10^{-4}$ M$_\odot$/yr should host no Type II supernova events. In addition, a specific list of initial stellar masses can be useful in numerical simulations of stellar systems. For the first time, we show optimally-sampled galaxy-wide IMFs (OSGIMF) which mimics the IGIMF with an additional serrated feature. Finally, A Python module, GalIMF, is provided allowing the calculation of the IGIMF and OSGIMF in dependence on the galaxy-wide SFR and metallicity.Comment: 15 pages, 15 figures, A&A, in press; paper remains unchanged (version1 equals version2); the GalIMF module is downloadable at githu

Nonlinear denoising of transient signals with application to event related potentials

We present a new wavelet based method for the denoising of {\it event related potentials} ERPs), employing techniques recently developed for the paradigm of deterministic chaotic systems. The denoising scheme has been constructed to be appropriate for short and transient time sequences using circular state space embedding. Its effectiveness was successfully tested on simulated signals as well as on ERPs recorded from within a human brain. The method enables the study of individual ERPs against strong ongoing brain electrical activity.Comment: 16 pages, Postscript, 6 figures, Physica D in pres

Self-Synchronization in Duty-cycled Internet of Things (IoT) Applications

In recent years, the networks of low-power devices have gained popularity. Typically these devices are wireless and interact to form large networks such as the Machine to Machine (M2M) networks, Internet of Things (IoT), Wearable Computing, and Wireless Sensor Networks. The collaboration among these devices is a key to achieving the full potential of these networks. A major problem in this field is to guarantee robust communication between elements while keeping the whole network energy efficient. In this paper, we introduce an extended and improved emergent broadcast slot (EBS) scheme, which facilitates collaboration for robust communication and is energy efficient. In the EBS, nodes communication unit remains in sleeping mode and are awake just to communicate. The EBS scheme is fully decentralized, that is, nodes coordinate their wake-up window in partially overlapped manner within each duty-cycle to avoid message collisions. We show the theoretical convergence behavior of the scheme, which is confirmed through real test-bed experimentation.Comment: 12 Pages, 11 Figures, Journa

SimpleTrack:Adaptive Trajectory Compression with Deterministic Projection Matrix for Mobile Sensor Networks

Some mobile sensor network applications require the sensor nodes to transfer their trajectories to a data sink. This paper proposes an adaptive trajectory (lossy) compression algorithm based on compressive sensing. The algorithm has two innovative elements. First, we propose a method to compute a deterministic projection matrix from a learnt dictionary. Second, we propose a method for the mobile nodes to adaptively predict the number of projections needed based on the speed of the mobile nodes. Extensive evaluation of the proposed algorithm using 6 datasets shows that our proposed algorithm can achieve sub-metre accuracy. In addition, our method of computing projection matrices outperforms two existing methods. Finally, comparison of our algorithm against a state-of-the-art trajectory compression algorithm show that our algorithm can reduce the error by 10-60 cm for the same compression ratio

Deterministic walks in random networks: an application to thesaurus graphs

In a landscape composed of N randomly distributed sites in Euclidean space, a walker (``tourist'') goes to the nearest one that has not been visited in the last \tau steps. This procedure leads to trajectories composed of a transient part and a final cyclic attractor of period p. The tourist walk presents universal aspects with respect to \tau and can be done in a wide range of networks that can be viewed as ordinal neighborhood graphs. As an example, we show that graphs defined by thesaurus dictionaries share some of the statistical properties of low dimensional (d=2) Euclidean graphs and are easily distinguished from random graphs. This approach furnishes complementary information to the usual clustering coefficient and mean minimum separation length.Comment: 12 pages, 5 figures, revised version submited to Physica A, corrected references to figure

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications