Successful completion of a cyclic ground test of a mercury ion auxiliary propulsion system

An engineering model Ion Auxiliary Propulsion System (IAPS) 8-cm thruster (S/N 905) has completed a life test at NASA Lewis Research Center. The mercury ion thruster successfully completed and exceeded the test goals of 2557 on/off cycles and 7057 hr of operation at full thrust. The final 1200 cycles and 3600 hr of the life test were conducted using an engineering model of the IAPS power electronics unit (PEU) and breadboard digital controller and interface unit (DCIU). This portion of the test is described in this paper with a charted history of thruster operating parameters and off-normal events. Performance and operating characteristics were constant throughout the test with only minor variations. The engineering model power electronics unit operated without malfunction; the flight software in the digital controller and interface unit was exercised and verified. Post-test inspection of the thruster revealed facility enhanced accelerator grid erosion but overall the thruster was in good condition. It was concluded that the thruster performance was not drastically degraded by time or cycles. Additional cyclic testing is currently under consideration

Low Power Dynamic Scheduling for Computing Systems

This paper considers energy-aware control for a computing system with two states: "active" and "idle." In the active state, the controller chooses to perform a single task using one of multiple task processing modes. The controller then saves energy by choosing an amount of time for the system to be idle. These decisions affect processing time, energy expenditure, and an abstract attribute vector that can be used to model other criteria of interest (such as processing quality or distortion). The goal is to optimize time average system performance. Applications of this model include a smart phone that makes energy-efficient computation and transmission decisions, a computer that processes tasks subject to rate, quality, and power constraints, and a smart grid energy manager that allocates resources in reaction to a time varying energy price. The solution methodology of this paper uses the theory of optimization for renewal systems developed in our previous work. This paper is written in tutorial form and develops the main concepts of the theory using several detailed examples. It also highlights the relationship between online dynamic optimization and linear fractional programming. Finally, it provides exercises to help the reader learn the main concepts and apply them to their own optimizations. This paper is an arxiv technical report, and is a preliminary version of material that will appear as a book chapter in an upcoming book on green communications and networking.Comment: 26 pages, 10 figures, single spac

Ultra-Low-Power Superconductor Logic

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux- Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count.Comment: 7 pages, 5 figure

Low Power, Low Delay: Opportunistic Routing meets Duty Cycling

Traditionally, routing in wireless sensor networks consists of two steps: First, the routing protocol selects a next hop, and, second, the MAC protocol waits for the intended destination to wake up and receive the data. This design makes it difficult to adapt to link dynamics and introduces delays while waiting for the next hop to wake up. In this paper we introduce ORW, a practical opportunistic routing scheme for wireless sensor networks. In a dutycycled setting, packets are addressed to sets of potential receivers and forwarded by the neighbor that wakes up first and successfully receives the packet. This reduces delay and energy consumption by utilizing all neighbors as potential forwarders. Furthermore, this increases resilience to wireless link dynamics by exploiting spatial diversity. Our results show that ORW reduces radio duty-cycles on average by 50% (up to 90% on individual nodes) and delays by 30% to 90% when compared to the state of the art

Capacitor Motor as Low-Power, Low-Speed Single-Phase Generator

In this paper, some results of experiment on modification of induction motor into generator are described. Not as usually done on three-phase motor, the modification has been done on capacitor motors normally supplied with single-phase source. The resulted induction generator should be able to self-excite and has been intended for low-power, low-speed applications. These applications are prospective for example in rural renewable energy generations and as motors for some special electric vehicles. Machine modification instead of total design-production or new machine acquisition is considered more appropriate for remote rural electrification. Distance and transportation difficulties, unavailability of nearby machine industry, lack of human resources with ‘high-tech savvy', besides the low purchasing power of population in remote rural areas are some reasons behind the consideration. Experiment results indicated that voltage generation up to nominal value is not always easy to attain in a capacitor motor, even when functioning beyond its synchronous speed. An additional pre-charged capacitor should be used to initiate voltage generation. During start-up, load and the pre-charged capacitor had to be removed from generator to avoid capacitor discharge. Load could then be added gradually once generator approached its nominal output value. It was also shown that in order to generate power the generator must be rotating over its synchronous speed. The resulted frequency values did not vary linearly to the rotation speed and the obtained efficiency was still low

Low power arcjet performance

An experimental investigation was performed to evaluate arc jet operation at low power. A standard, 1 kW, constricted arc jet was run using nozzles with three different constrictor diameters. Each nozzle was run over a range of current and mass flow rates to explore stability and performance in the low power engine. A standard pulse-width modulated power processor was modified to accommodate the high operating voltages required under certain conditions. Stable, reliable operation at power levels below 0.5 kW was obtained at efficiencies between 30 and 40 percent. The operating range was found to be somewhat dependent on constrictor geometry at low mass flow rates. Quasi-periodic voltage fluctuations were observed at the low power end of the operating envelope, The nozzle insert geometry was found to have little effect on the performance of the device. The observed performance levels show that specific impulse levels above 350 seconds can be obtained at the 0.5 kW power level

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.Comment: 8 Pages, VLSICS Journa

Parametric Reliability of Low Power Adiabatic SRAM

This paper presents our attempt to recover back energy that is stored in the bit lines and in the cell and reused it by a phenomenal technique of energy recovery known as adiabatic principles. By the application of this adiabatic driver the loss of energy to the ground during ‘1\u27to‘0\u27 transition in SRAM is reduced to a greater degree. In this paper the performance of the conventional 6T SRAM circuit is compared with the performance of the Adiabatic 6T SRAM. In the adiabatic SRAM good high degree of power reduction is reported. By applying the aforementioned technique same SRAM is investigated by varying technology. Another parameter such as delay and power delay product (PDP) is also been calculated for all the SRAM. All the circuits are simulated in HSPICE and delay is calculated using Cosmo scope

Powertrace: Network-level Power Profiling for Low-power Wireless Networks

Low-power wireless networks are quickly becoming a critical part of our everyday infrastructure. Power consumption is a critical concern, but power measurement and estimation is a challenge. We present Powertrace, which to the best of our knowledge is the first system for network-level power profiling of low-power wireless systems. Powertrace uses power state tracking to estimate system power consumption and a structure called energy capsules to attribute energy consumption to activities such as packet transmissions and receptions. With Powertrace, the power consumption of a system can be broken down into individual activities which allows us to answer questions such as “How much energy is spent forwarding packets for node X?”, “How much energy is spent on control traffic and how much on critical data?”, and “How much energy does application X account for?”. Experiments show that Powertrace is accurate to 94% of the energy consumption of a device. To demonstrate the usefulness of Powertrace, we use it to experimentally analyze the power behavior of the proposed IETF standard IPv6 RPL routing protocol and a sensor network data collection protocol. Through using Powertrace, we find the highest power consumers and are able to reduce the power consumption of data collection with 24%. It is our hope that Powertrace will help the community to make empirical energy evaluation a widely used tool in the low-power wireless research community toolbox

Low Power Explicit Pulse Triggered Flip-Flop Design Based On A Pass Transistor

In VLSI system design, power consumption is the ambitious issue for the past respective years. Advanced IC fabrication technology grants the use of nano scaled devices, so the power dissipation becomes major problem in the designing of VLSI chips. In this paper we present, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme using pass transistor. The offered design successfully figure out the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better power performance by consuming low power. The proposed design also significantly reduces delay time, set-up time and hold time. Simulation results based on TMC 180nm CMOS technology reveal that the proposed design features the best power and delay performance in several FF designs under comparison