USING LOGIC SYNTHESIS TOOLS FOR TEXAS INSTRUMENTS FP GAs

High density PLDs (Programmable Logic Devices) and FP GAs (Field-Programmable Gate Arrays) are becoming more and more popular in the field of logic design. Their ultimate advantages - no NRE (Non-REcurring) costs, fast time-to-market, in-house design, etc. - are being combined with ever increasing speeds and densities. Up to now the tradi- tional FPGA design technique has been schematics. But hardware complexity has outrun schematics with chips so complex that the graphical representation of the circuit shows only a web of connectivity, not the functionality of the design. For this reason more and more engineers are turning to Hardware Description Languages (HDL) for digital design. The prospect of using Logic Synthesis Tools is one of the main reasons which make HDLs attractive for designers. These tools take a behavioural, or other type of HDL description, and produce a technology specific net list for an FPGA or for another type of ASIC. The effectiveness of the Logic Synthesis Tools is a key factor in deciding against or in favour of HDLs and synthesis. The synthesis powers of two programs were tested and compared using three sample designs. The meaning of FPGAs, HDLs and Logic Synthesis are ex- plained in more detail in the first chapters of the article. The results of logic synthesis are in the second part. The source codes, command line arguments and batch (or script) files used are also given

Hardware Descriptive Languages: An Efficient Approach to Device Independent Designs with Complex Programmable Logic Devices and Field Programmable Gate Arrays

Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog and consequently target it to Complex programmable logic devices (CPLDs) and Field programmable gate arrays (FPGAs). If this is properly implemented, it will reduce bulkiness of most of the presently used electronic and electrical devices in our technology This paper will focus on using VHDL to design an application specific integrated circuit (ASIC) liquid dispenser controller system while targeting the device independent architecture (Ultra 3700 CPLD series) for synthesis, optimization and fitting to realize the design. The ASIC controller will have two bin cans to dispense regular and diet drinks. The system will dispense a drink if the user activates a button for that drink and at least one can is available. A refill signal appears when both bins are empty. Activating a reset signal informs the system that the machine has been refilled and the bins are full. The design methodology is presented with other details in the body of this paper.Keywords: Very high speed integrated circuit hardware descriptive language (VHDL); Application Specific Integrated Circuit; Synthesis (ASIC); Complex programmable logic devices (CPLDs); field programmable gate arrays (FPGAs

An introductory digital design course using a low–cost autonomous robot

This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor–transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot

Efficient VHDL models for various PLD architectures

VHDL is a flexible language for programming PLDs (Programmable Logic Devices) but the way it is synthesized for different architectures varies. Since there are several types of PLDs and several synthesis tools, it is very important for the designer to know which VHDL model to use for a particular architecture in order to achieve maximum efficiency. The term efficiency refers to a good use of resources that result to a denser fit of the logic design into the PLD with a minimum implementation delay. The choice of the VHDL model also depends on the application and the expectations of the designer. Based on the information from several PLD architectures, this thesis points out the maximum efficiency models for each architecture in different aspects of VHDL programming and sequential logic applications. The architectures that the study is focused on, are the Altera MAX family and the Cypress MAX, Flash and CY7C33x families

A survey of DA techniques for PLD and FPGA based systems

Programmable logic devices (PLDs) are gaining in acceptance, of late, for designing systems of all complexities ranging from glue logic to special purpose parallel machines. Higher densities and integration levels are made possible by the new breed of complex PLDs and FPGAs. The added complexities of these devices make automatic computer aided tools indispensable for achieving good performance and a high usable gate-count. In this article, we attempt to present in an unified manner, the different tools and their underlying algorithms using an example of a vending machine controller as an illustrative example. Topics covered include logic synthesis for PLDs and FPGAs along with an in-depth survey of important technology mapping, partitioning and place and route algorithms for different FPGA architectures.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/31206/1/0000108.pd

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized