Hands-on Learning in Multiple Courses in Electrical and Computer Engineering

It has been reported that persistence rate of engineering students is relatively low. Several new pedagogical paradigms have been proposed to improve engineering education, such as the use of “hands-on” tools to change the learning style in the engineering classroom to more engaging teaching pedagogies. An approach that is being used to engage and retain electrical and computer engineering students is the Analog Discovery board (ADB). The paper describes the hands-on learning experiences of students who used the ADB in multiple courses. The paper discusses (i) the various laboratory experiments and class projects performed by the students, (ii) the knowledge and skills learnt by the students and (iii) the lessons learnt by the instructors while introducing ADB into freshman and junior level courses in the electrical and computer engineering. Preliminary data indicate that students are benefiting from the use of the ADB. Students report increases in their interest in subject content, motivation to learn, and confidence in their ability to learn.Cockrell School of Engineerin

Nonphotolithographic nanoscale memory density prospects

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Array-based architecture for FET-based, nanoscale electronics

Advances in our basic scientific understanding at the molecular and atomic level place us on the verge of engineering designer structures with key features at the single nanometer scale. This offers us the opportunity to design computing systems at what may be the ultimate limits on device size. At this scale, we are faced with new challenges and a new cost structure which motivates different computing architectures than we found efficient and appropriate in conventional very large scale integration (VLSI). We sketch a basic architecture for nanoscale electronics based on carbon nanotubes, silicon nanowires, and nano-scale FETs. This architecture can provide universal logic functionality with all logic and signal restoration operating at the nanoscale. The key properties of this architecture are its minimalism, defect tolerance, and compatibility with emerging bottom-up nanoscale fabrication techniques. The architecture further supports micro-to-nanoscale interfacing for communication with conventional integrated circuits and bootstrap loading

Designing with Iontronic Logic Gates -- From a Single Polyelectrolyte Diode to Small Scale Integration

This article presents the implementation of on-chip iontronic circuits via small-scale integration of multiple ionic logic gates made of bi-polar polyelectrolyte diodes. These ionic circuits are analogous to solid-state electronic circuits, with ions as the charge carriers instead of electrons/holes. We experimentally characterize the responses of a single fluidic diode made of a junction of oppositely charged polyelectrolytes (i.e., anion and cation exchange membranes), with a similar underlying mechanism as a solid-state p- and n-type junction. This served to carry out pre-designed logical computations in various architectures by integrating multiple diode-based logic gates, where the electrical signal between the integrated gates was transmitted entirely through ions. The findings shed light on the limitations affecting the number of logic gates that can be integrated, the degradation of the electrical signal, their transient response, and the design rules that can improve the performance of iontronic circuits

電荷貯蔵材料としてのラジカル置換ポリマーとそのレドックスメディエーションに基づく電荷輸送

早大学位記番号:新7511早稲田大

Thermomass Theory: A Mechanical Pathway to Analyze Anomalous Heat Conduction in Nanomaterials

The synthesis and measurements of nanomaterials have yielded significant advances in the past decades. In the area of thermal conduction, the nanomaterials exhibit anomalous behavior such as size-dependent thermal conductivity, thermal rectification, and ultra-high thermoelectric properties. The theoretical understanding and modeling on these behaviors are much desired. In this chapter, we study the thermal conduction in nanomaterials through the thermomass theory, which models the heat transfer from a fluid mechanics viewpoint. The control equations of the equivalent mass of the thermal energy are formulated following the continuum mechanics principles, which give the general heat conduction law. It incorporates nonlinear effects such as spatial acceleration and boundary resistance, which can overcome the drawbacks of the traditional Fourier’s law in nanoscale systems. By the thermomass theory, we successfully model the size-dependent effective thermal conductivity in nanosystems. Furthermore, the thermal rectification as well as the thermoelectric enhancement in nanosystems is also discussed with the present framework

Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches

Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048 x 2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 10^11 b/cm^2

Molecular Electronics

Molecular electronics describes the field in which molecules are utilized as the active (switching, sensing, etc.) or passive (current rectifiers, surface passivants) elements in electronic devices. This review focuses on experimental aspects of molecular electronics that researchers have elucidated over the past decade or so and that relate to the fabrication of molecular electronic devices in which the molecular components are readily distinguished within the electronic properties of the device. Materials, fabrication methods, and methods for characterizing electrode materials, molecular monolayers, and molecule/electrode interfaces are discussed. A particular focus is on devices in which the molecules or molecular monolayer are sandwiched between two immobile electrodes. Four specific examples of such devices, in which the electron transport characteristics reflect distinctly molecular properties, are discussed

Three-way electrical gating characteristics of metallic Y-junction carbon nanotubes

Y-junction based carbon nanotube (CNT) transistors exhibit interesting switching behaviors, and have the structural advantage that the electrical gate for current modulation can be formed by any of the three constituent branches. In this letter, we report on the gating characteristics of metallic Y-CNT morphologies. By measuring the output conductance and transconductance we conclude that the efficiency and gain depend on the branch diameter and is electric field controlled. Based on these principles, we propose a design for a Y-junction based CNT switching device, with tunable electrical properties