LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

A Survey of Digital Systems Curriculum and Pedagogy in Electrical and Computer Engineering Programs

Digital Systems is one of the basic foundational courses in Electrical and Computer Engineering. One of the challenges in designing and modifying the curriculum for the course is the fast pace of technology change in the area. TTL chips that were in vogue with students building physical circuits, have given way to new paradigms like FPGA based synthesis with hardware description languages such as VHDL. However, updating a course is not as simple as just changing the book, and changing the syllabus. A large amount of work needs to be done in terms of selecting the book that will accommodate the course, the device that should be used, the laboratory content, and even how much time needs to be dedicated for every topic. All these issues, and many more makes it hard to take the decision of updating the course. For that reason, this paper surveys the pedagogy and methodology that is used to teach the digital systems curriculum at different universities. The goal is that it will serve as a resource for faculty looking to update or revamp their digital systems curricula. Within the document they will find a comparative study by electrical and computer engineering program, a list of textbooks, and the devices most commonly used.Cockrell School of Engineerin

Integrating a nanologic knowledge module Into an undergraduate logic design course

This work discusses a knowledge module in an undergraduate logic design course for electrical engineering (EE) and computer science (CS) students, that introduces them to nanocomputing concepts. This knowledge module has a twofold objective. First, the module interests students in the fundamental logical behavior and functionality of the nanodevices of the future, which will motivate them to enroll in other elective courses related to nanotechnology, offered in most EE and CS departments. Second, this module can be used to let students analyze, synthesize, and apply their existing knowledge of the Karnaugh-map-based Boolean logic reduction scheme into a revolutionary design context with majority logic. Where many efforts focus on developing new courses on nanofabrication and even nanocomputing, this work is designed to augment the existing standard EE and CS courses by inserting knowledge modules on nanologic structures so as to stimulate student interest without creating a significant diversion from the course framework

ORDERING THE MOST RELEVANT SKILLS IN AN ENGINEERING DEGREE USING FUZZY LOGIC. A CASE STUDY

Nowadays, the increasing uncertainty of a globalized world economy poses additional challenges to the new agricultural engineering graduates. They have to face increasingly complex challenges, such as increasing demand for agricultural produce in a Climate Change situation, a growing difficulty to guarantee food safety caused by global trade, and an improvement of the resilience of productive systems based on precision agriculture. All of this along with the drawback of a reduced interest of new students in this kind of graduate study. Previous works have dealt with the importance of the general skills in an agricultural engineering degree, showing the relevance of the instrumental skills (capacity for analysis and synthesis, organization and planning capacity, ability to manage information, oral and written communication, foreign language knowledge, computer knowledge, problem resolution, and decision making). This work aims to order these instrumental skills to face the above-mentioned challenges in a more effective way. We are aware that the result of this order presents high doses of uncertainty and ambiguity, and that is why we propose the use of fuzzy logic. The application of this methodology based on fuzzy mathematics can contribute to updating the university degrees so that graduates can successfully the new challenges they will encounter in the workplace. Results show that capacity for analysis and synthesis, organization and planning capacity, and foreign language knowledge is the best-considered skill

Work in progress: introduction of K-map based nano-logic synthesis as knowledge module in logic design course

This work in progress reports an effort of introducing knowledge module regarding novel nano-devices and novel logic primitives in undergraduate logic design class. Our motivation is to make our students aware of fundamental abstracted logical behaviors of future nano-devices, their functionality. This effort would also help the students use their existing knowledge of K-map based logical synthesis into constructing logic blocks for novel devices that uses majority logic as basic construct. Moreover, additional to stimulating our students' interests, we are also augmenting their learning by challenging them to use their existing knowledge to analyze, synthesize and comprehend novel nano-logic issues through the worksheets and lecture modules. Whereas many efforts are focusing on developing new courses on nanofabrication and even nano-computing, we intend to augment the existing standard EE and CS courses by inserting knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework

Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel

High-level synthesis (HLS) allows hardware designers to think algorithmically and not worry about low-level, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoffs between resource utilization and performance. Unfortunately, security evaluation is not a standard part of the HLS design flow. In this article, we aim to understand the effects of memory-based HLS optimizations on power side-channel leakage. We use Xilinx Vivado HLS to develop different cryptographic cores, implement them on a Spartan-6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and information leakage through power consumption. We have two important observations and contributions. First, the choice of resource optimization directive results in different levels of side-channel vulnerabilities. Second, the partitioning optimization directive can greatly compromise the hardware cryptographic system through power side-channel leakage due to the deployment of memory control logic. We describe an evaluation procedure for power side-channel leakage and use it to make best-effort recommendations about how to design more secure architectures in the cryptographic domain