Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

A Framework for Verification of Signal Propagation Through Sequential Nanomagnet Logic Devices

Nanomagnet Logic is an emerging technology for low-power, highly-scalable implementation of quantum-dot cellular automata. Feedback permits reuse of logical subroutines, which is a desired functionality of any computational device. Determining whether feedback is feasible is essential to assessing the robustness of nanomagnet logic in any pipelined computing design. Therefore, development of a quantitative approach for verification of feedback paths is critical for development of design and synthesis tools for nanomagnet logic structures. In this paper, a framework for verification of sequential nanomagnet logic devices is presented. A set of definitions for canonical alignment and state definitions for NML paths are presented, as well as mathematical operations for determining the resulting states. The simulation results are presented for quantification of the NML magnetization angles for horizontal, vertical, negative-diagonal, and positive diagonal geometric alignments. The presented framework may be used as the basis for defining a representation of signal propagation for design and verification for robust NML devices and preventing deadlock resulting from improper implementation

DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction

Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.Comment: 15 pages, 14 figures, to appear IEICE Trans. Fundamentals, Vol. E91-A, No.1

A design environment for synthesis of embedded fuzzy controllers on FPGAs

This paper presents a design environment for the synthesis of embedded fuzzy controllers on FPGAs. It provides a novel implementation technique that allows accelerating the exploration of the design space of fuzzy control modules, as well as a codesign flow that eases their integration into complex control systems and the joint development of hardware and software components. The set of CAD tools supporting this environment includes specific fuzzy logic design tools provided by Xfuzzy, FPGA synthesis and implementation tools from Xilinx, and modeling and simulation facilities from Matlab. As demonstrated by the analyzed design examples, the described development strategy takes advantage of flexibility and ease of configuration offered by the different tools to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy control system

DESIGN METHODOLOGIES AND SOME ASPECTS OF VLSI AND ULSI

This is a review and considers first technical aspects and drawbacks for realizing very large scale and wafer scale integrated circuits. Among these are small geometry effects and interconnection delay. Some solutions are considered. Next, design methodologies for VLSI are discussed, considering the hierarchy of VLSI systems. Finally the influences for students education are remarked and a design system consisting of CAD tools for logic synthesis and simulation, network-and device simulation, automated layout generation and layout-verification are described

Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B

Modern System-on-chip (SoC) hardware design puts considerable pressure on existing design and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for efficient architectural exploration and re-use. The existing methods for taking a high-level paper specification and refining this specification to an implementation that meets its performance criteria is largely manual and error-prone and as RTL descriptions get larger, a systematic design method is necessary to address explicitly the timing issues that arise when applying logic synthesis to such large blocks.Guarded Atomic Actions have been shown to offer a convenient notation for describing microarchitectures that is amenable to formal reasoning and high-level synthesis. Event-B is a language and method that supports the development of specifications with automatic proof and refinement, based on guarded atomic actions. Latency-insensitive design ensures that a design composed of functionally correct components will be independent of communication latency. A method has been developed which uses Event-B for latency-insensitive SoC component and sub-system design which can be combined with high-level, component synthesis to enable architectural exploration and re-use at the specification level and to close the specification gap in the SoC hardware flow