2 research outputs found
Logic minimization and testability of 2SPP-P-Circuits
We investigate a form of logic decomposition that generates a 2SPP-P-circuit,
which includes two blocks representing the projected subfunctions
obtained by Shannon cofactoring with respect to a chosen variable,
and a block representing the intersection of the projections.
The three blocks are implemented as minimal 2-SPP forms (XOR-AND-OR with
XOR restricted to two inputs).
The minimization is performed using as don't care set the points in the
intersection of the projections.
This structure can be used in synthesis for low power or low delay,
to move critical signals (e.g., with highest switching activity)
toward the outputs with minimum area penalty.
We prove an estimate by which the area of a 2SPP-P-circuit has at most
twice the terms than its equivalent standard 2-SPP circuit (with
no Shannon cofactoring).
We also argue that the procedure delivers a circuit (when augmented
with a pair of multiplexers) fully testable under the single stuck-at-fault
model.
We implemented the proposed synthesis procedure and we present
encouraging results compared with standard 2-SPPs and SOPs
LOGIC MINIMIZATION AND TESTABILITY OF 2SPP-P-CIRCUITS
We investigate a form of logic decomposition that generates a 2SPP-P-circuit, which includes two blocks representing the projected subfunctions obtained by Shannon cofactoring with respect to a chosen variable, and a block representing the intersection of the projections. The three blocks are implemented as minimal 2-SPP forms (XOR-ANDOR with XOR restricted to two inputs). The minimization is performed using as don't care set the points in the intersection of the projections. This structure can be used in synthesis for low power or low delay, to move critical signals (e.g., with highest switching activity) toward the outputs with minimum area penalty. We prove an estimate by which the area of a 2SPP-P-circuit has at most twice the terms than its equivalent standard 2-SPP circuit (with no Shannon cofactoring). We also argue that the procedure delivers a circuit (when augmented with a pair of multiplexers) fully testable under the single stuck-at-fault model. We implemented the proposed synthesis procedure and we present encouraging results compared with standard 2-SPPs and SOPs