A timing optimization method based on clock skew scheduling and partitioning in a parallel computing environment

Paper presented at the Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico.This paper describes the implementation of a heuristic method to perform non-zero clock skew scheduling of digital VLSI circuits in a parallel computing environment. In the proposed method, circuit partitions that have low number of timing paths between partitions are formed. Clock skew scheduling is applied independently to each partition-sequentially or in parallel on a computing cluster-and results are iteratively merged. The scalability of the proposed method is superior compared to conventional non-zero clock skew scheduling techniques due to the reduction of analyzed circuit sizes (partition sizes) at each iteration step and the potential to parallelize the analyses of these partitions. It is demonstrated that after only the first iteration step of the proposed method, feasible clock schedules for 65% of the ISCAS'89 benchmark circuits are computed. For these circuits, average speedups of 2.1X and 2.6X are observed for sequential and parallel application of clock skew scheduling to partitions, respectively

Timing-driven physical design for VLSI circuits using resonant rotary clocking

Paper presented at the Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico.Resonant clocking technologies are next-generation clocking technologies that provide low or controllable-skew, low-jitter and multi-gigahertz frequency clock signals with low power consumption. This paper describes a collection of circuit partitioning, placement and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with the resonant rotary clocking technology. Resonant rotary clocking technology inherently supports (and requires) non-zero clock skew operation, which permits further improved circuit performances. The proposed physical design flow entails integrated circuit partitioning and placement methodologies that permit the hierarchical application of non-zero clock skew system timing. This design flow is shown to be a computationally efficient implementation method

Advanced Timing and Synchronization Methodologies for Digital VLSI Integrated Circuits

This dissertation addresses timing and synchronization methodologies that are critical to the design, analysis and optimization of high-performance, integrated digital VLSI systems. As process sizes shrink and design complexities increase, achieving timing closure for digital VLSI circuits becomes a significant bottleneck in the integrated circuit design flow. Circuit designers are motivated to investigate and employ alternative methods to satisfy the timing and physical design performance targets. Such novel methods for the timing and synchronization of complex circuitry are developed in this dissertation and analyzed for performance and applicability.Mainstream integrated circuit design flow is normally tuned for zero clock skew, edge-triggered circuit design. Non-zero clock skew or multi-phase clock synchronization is seldom used because the lack of design automation tools increases the length and cost of the design cycle. For similar reasons, level-sensitive registers have not become an industry standard despite their superior size, speed and power consumption characteristics compared to conventional edge-triggered flip-flops.In this dissertation, novel design and analysis techniques that fully automate the design and analysis of non-zero clock skew circuits are presented. Clock skew scheduling of both edge-triggered and level-sensitive circuits are investigated in order to exploit maximum circuit performances. The effects of multi-phase clocking on non-zero clock skew, level-sensitive circuits are investigated leading to advanced synchronization methodologies. Improvements in the scalability of the computational timing analysis process with clock skew scheduling are explored through partitioning and parallelization.The integration of the proposed design and analysis methods to the physical design flow of integrated circuits synchronized with a next-generation clocking technology-resonant rotary clocking technology-is also presented. Based on the design and analysis methods presented in this dissertation, a computer-aided design tool for the design of rotary clock synchronized integrated circuits is developed