277 research outputs found
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Όλ¬Έ (λ°μ¬)-- μμΈλνκ΅ λνμ : μ κΈ°Β·μ»΄ν¨ν°κ³΅νλΆ, 2016. 2. κΉμ§ν.Replacing HDDs with NAND flash-based storage devices (SSDs) has been one of the major challenges in modern computing systems especially in regards to better performance and higher mobility. Although uninterrupted semiconductor process scaling and multi-leveling techniques lower the price of SSDs to the comparable level of HDDs, the decreasing lifetime of NAND flash memory, as a side effect of recent advanced device technologies, is emerging as one of the major barriers to the wide adoption of SSDs in high-performance computing systems.
In this dissertation, we propose new cross-layer optimization techniques to extend the lifetime (in particular, endurance) of NAND flash memory. Our techniques are motivated by our key observation that erasing a NAND block with a lower voltage or at a slower speed can significantly improve NAND endurance. However, using a lower voltage in erase operations causes adverse side effects on other NAND characteristics such as write performance and retention capability. The main goal of the proposed techniques is to improve NAND endurance without affecting the other NAND requirements.
We first present Dynamic Erase Voltage and Time Scaling (DeVTS), a unified framework to enable a system software to exploit the tradeoff relationship between the endurance and erase voltages/times of NAND flash memory. DeVTS includes erase voltage/time scaling and write capability tuning, each of which brings a different impact on the endurance, performance, and retention capabilities of NAND flash memory.
Second, we propose a lifetime improvement technique which takes advantage of idle times between write requests when erasing a NAND block with a slower speed or when writing data to a NAND block erased with a lower voltage. We have implemented a DeVTS-enabled FTL, called dvsFTL, which optimally adjusts the erase voltage/time and write performance of NAND devices in an automatic fashion. Our experimental results show that dvsFTL can improve NAND endurance by 62%, on average, over DeVTS-unaware FTL with a negligible decrease in the overall write performance.
Third, we suggest a comprehensive lifetime improvement technique which exploits variations of the retention requirements as well as the performance requirement of SSDs when writing data to a NAND block erased with a lower voltage. We have implemented dvsFTL+, an extended version of dvsFTL, which fully utilizes DeVTS by accurately predicting the write performance and retention requirements during run times. Our experimental results show that dvsFTL+ can further improve NAND endurance by more than 50% over dvsFTL while preserving all the NAND requirements.
Lastly, we present a reliability management technique which prevents retention failure problems when aggressive retention-capability tuning techniques are employed in real environments. Our measurement results show that the proposed technique can recover corrupted data from retention failures up to 23 times faster over existing data recovery techniques. Furthermore, it can successfully recover severely retention-failed data, such as ones experienced 8 times longer retention times than the retention-time specification, that were not recoverable with the existing technique.
Based on the evaluation studies for the developed lifetime improvement techniques, we verified that the cross-layer optimization approach has a significant impact on extending the lifetime of NAND flash-based storage devices. We expect that our proposed techniques can positively contribute to not only the wide adoption of NAND flash memory in datacenter environments but also the gradual acceleration of using flash as main memory.Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Dissertation Goals 3
1.3 Contributions 4
1.4 Dissertation Structure 5
Chapter 2 Background 7
2.1 Threshold Voltage Window of NAND Flash Memory 7
2.2 NAND Program Operation 10
2.3 Related Work 11
2.3.1 System-Level SSD Lifetime Improvement Techniques 12
2.3.2 Device-Level Endurance-Enhancing Technique 15
2.3.3 Cross-Layer Optimization Techniques Exploiting NAND Tradeoffs 17
Chapter 3 Dynamic Erase Voltage and Time Scaling 20
3.1 Erase Voltage and Time Scaling 22
3.1.1 Motivation 22
3.1.2 Erase Voltage Scaling 23
3.1.3 Erase Time Scaling 26
3.2 Write Capability Tuning 28
3.2.1 Write Performance Tuning 29
3.2.2 Retention Capability Tuning 30
3.2.3 Disturbance Resistance Tuning 33
3.3 NAND Endurance Model 34
Chapter 4 Lifetime Improvement Technique Using Write-Performance Tuning 39
4.1 Design and Implementation of dvsFTL 40
4.1.1 Overview 40
4.1.2 Write-Speed Mode Selection 41
4.1.3 Erase Voltage Mode Selection 44
4.1.4 Erase Speed Mode Selection 46
4.1.5 DeVTS-wPT Aware FTL Modules 47
4.2 Experimental Results 50
4.2.1 Experimental Settings 50
4.2.2 Workload Characteristics 53
4.2.3 Endurance Gain Analysis 54
4.2.4 Overall Write Throughput Analysis 56
4.2.5 Detailed Analysis 58
Chapter 5 Lifetime Improvement Technique Using Retention-Capability Tuning 60
5.1 Design and Implementation of dvsFTL+ 62
5.1.1 Overview 62
5.1.2 Retention Requirement Prediction 64
5.1.3 Maximization of Endurance Benefit 66
5.1.4 Minimization of Reclaim Overhead 68
5.2 Experimental Results 69
5.2.1 Experimental Settings 69
5.2.2 Workload Characteristics 70
5.2.3 Endurance Gain Analysis 72
5.2.4 NAND Requirements Analysis 73
5.2.5 Detailed Analysis of Retention-Time Predictor 76
5.2.6 Detailed Analysis of Endurance Gain 83
Chapter 6 Reliability Management Technique for NAND Flash Memory 87
6.1 Overview 89
6.2 Motivation 91
6.2.1 Limitations of the Existing Retention-Error Management Policy 91
6.2.2 Limitations of the Existing Retention-Failure Recovery Technique 92
6.3 Retention Error Recovery Technique 95
6.3.1 Charge Movement Model 95
6.3.2 A Selective Error-Correction Procedure 99
6.3.3 Implementation 100
6.4 Experimental Results 103
Chapter 7 Conclusions 108
7.1 Summary and Conclusions 108
7.2 Future Work 110
7.2.1 Lifetime Improvement Technique Exploiting The Other NAND Tradeoffs 110
7.2.2 Development of Extended Techniques for DRAM-Flash Hybrid Main Memory Systems 111
7.2.3 Development of Specialized SSDs 112
Bibliography 114
μ΄ λ‘ 122Docto
Increasing Flash Memory Lifetime by Dynamic Voltage Allocation for Constant Mutual Information
The read channel in Flash memory systems degrades over time because the
Fowler-Nordheim tunneling used to apply charge to the floating gate eventually
compromises the integrity of the cell because of tunnel oxide degradation.
While degradation is commonly measured in the number of program/erase cycles
experienced by a cell, the degradation is proportional to the number of
electrons forced into the floating gate and later released by the erasing
process. By managing the amount of charge written to the floating gate to
maintain a constant read-channel mutual information, Flash lifetime can be
extended. This paper proposes an overall system approach based on information
theory to extend the lifetime of a flash memory device. Using the instantaneous
storage capacity of a noisy flash memory channel, our approach allocates the
read voltage of flash cell dynamically as it wears out gradually over time. A
practical estimation of the instantaneous capacity is also proposed based on
soft information via multiple reads of the memory cells.Comment: 5 pages. 5 figure
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Όλ¬Έ(λ°μ¬) -- μμΈλνκ΅λνμ : 곡과λν μ»΄ν¨ν°κ³΅νλΆ, 2021.8. κΉμ§ν.The development of ultra-large NAND flash storage devices (SSDs) is recently made possible by NAND flash memory semiconductor process scaling and multi-leveling techniques, and NAND package technology, which enables continuous increasing of storage capacity by mounting many NAND flash memory dies in an SSD.
As the capacity of an SSD increases, the total cost of ownership of the storage system can be reduced very effectively, however due to limitations of ultra-large SSDs in reliability and performance,
there exists some obstacles for ultra-large SSDs to be widely adopted.
In order to take advantage of an ultra-large SSD, it is necessary to develop new techniques to improve these reliability and performance issues.
In this dissertation, we propose various optimization techniques to solve the reliability and performance issues of ultra-large SSDs. In order to overcome the optimization limitations of the existing approaches, our techniques were designed based on various characteristic evaluation results of NAND flash devices and field failure characteristics analysis results of real SSDs.
We first propose a low-stress erase technique for the purpose of reducing the characteristic deviation between wordlines (WLs) in a NAND flash block. By reducing the erase stress on weak WLs, it effectively slows down NAND degradation and improves NAND endurance. From the NAND evaluation results, the conditions that can most effectively guard the weak WLs are defined as the gerase mode. In addition, considering the user workload characteristics, we propose a technique to dynamically select the optimal gerase mode that can maximize the lifetime of the SSD.
Secondly, we propose an integrated approach that maximizes the efficiency of copyback operations to improve performance while not compromising data reliability.
Based on characterization using real 3D TLC flash chips, we propose a novel per-block error propagation model under consecutive copyback operations. Our model significantly increases the number of successive copybacks by exploiting the aging characteristics of NAND blocks. Furthermore, we devise a resource-efficient error management scheme that can handle successive copybacks where pages move around multiple blocks with different reliability.
By utilizing proposed copyback operation for internal data movement, SSD performance can be effectively improved without any reliability issues.
Finally, we propose a new recovery scheme, called reparo, for a
RAID storage system with ultra-large SSDs. Unlike the existing RAID recovery schemes, reparo repairs a failed SSD at the NAND die granularity without replacing it with a new SSD, thus avoiding most of the inter-SSD data copies during a RAID recovery step.
When a NAND die of an SSD fails, reparo exploits a multi-core processor of the SSD controller to identify failed LBAs from the failed NAND die and to recover data from the failed LBAs. Furthermore, reparo ensures no negative post-recovery impact on the performance and lifetime of the repaired SSD.
In order to evaluate the effectiveness of the proposed techniques, we implemented them in a storage device prototype, an open NAND flash storage device development environment, and a real SSD environment. And their usefulness was verified using various benchmarks and I/O traces collected the from real-world applications.
The experiment results show that the reliability and performance of the ultra-large SSD can be effectively improved through the proposed techniques.λ°λ체 곡μ μ λ―ΈμΈν, λ€μΉν κΈ°μ μ μν΄μ μ§μμ μΌλ‘ μ©λμ΄ μ¦κ°νκ³ μλ λ¨μ λΈλ νλμ¬ λ©λͺ¨λ¦¬μ νλμ λΈλ νλμ¬ κΈ°λ° μ€ν λ¦¬μ§ μμ€ν
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λΈλ νλμ¬μ μ νλ μΉ΄νΌλ°±(copyback) λͺ
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λ§μ§λ§μΌλ‘, λ³Έ λ
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λ° κ³΅κ° λΈλ νλμ¬ μ μ₯μ₯μΉ κ°λ°νκ²½, κ·Έλ¦¬κ³ μ€μ₯ SSDνκ²½μ ꡬνλμμΌλ©°,
μ€μ μμ© νλ‘κ·Έλ¨μ λͺ¨μ¬ν λ€μν λ²€νΈλ§ν¬ λ° μ€μ I/O νΈλ μ΄μ€λ€μ μ΄μ©νμ¬ κ·Έ μ μ©μ±μ κ²μ¦νμλ€.
μ€ν κ²°κ³Ό, μ μλ κΈ°λ²λ€μ ν΅ν΄μ μ΄κ³ μ©λ SSDμ μ λ’°μ± λ° μ±λ₯μ ν¨κ³Όμ μΌλ‘ κ°μ ν μ μμμ νμΈνμλ€.I Introduction 1
1.1 Motivation 1
1.2 Dissertation Goals 3
1.3 Contributions 5
1.4 Dissertation Structure 8
II Background 11
2.1 Overview of 3D NAND Flash Memory 11
2.2 Reliability Management in NAND Flash Memory 14
2.3 UL SSD architecture 15
2.4 Related Work 17
2.4.1 NAND endurance optimization by utilizing page characteristics difference 17
2.4.2 Performance optimizations using copyback operation 18
2.4.3 Optimizations for RAID Rebuild 19
2.4.4 Reliability improvement using internal RAID 20
III GuardedErase: Extending SSD Lifetimes by Protecting Weak Wordlines 22
3.1 Reliability Characterization of a 3D NAND Flash Block 22
3.1.1 Large Reliability Variations Among WLs 22
3.1.2 Erase Stress on Flash Reliability 26
3.2 GuardedErase: Design Overview and its Endurance Model 28
3.2.1 Basic Idea 28
3.2.2 Per-WL Low-Stress Erase Mode 31
3.2.3 Per-Block Erase Modes 35
3.3 Design and Implementation of LongFTL 39
3.3.1 Overview 39
3.3.2 Weak WL Detector 40
3.3.3 WAF Monitor 42
3.3.4 GErase Mode Selector 43
3.4 Experimental Results 46
3.4.1 Experimental Settings 46
3.4.2 Lifetime Improvement 47
3.4.3 Performance Overhead 49
3.4.4 Effectiveness of Lowest Erase Relief Ratio 50
IV Improving SSD Performance Using Adaptive Restricted- Copyback Operations 52
4.1 Motivations 52
4.1.1 Data Migration in Modern SSD 52
4.1.2 Need for Block Aging-Aware Copyback 53
4.2 RCPB: Copyback with a Limit 55
4.2.1 Error-Propagation Characteristics 55
4.2.2 RCPB Operation Model 58
4.3 Design and Implementation of rcFTL 59
4.3.1 EPM module 60
4.3.2 Data Migration Mode Selection 64
4.4 Experimental Results 65
4.4.1 Experimental Setup 65
4.4.2 Evaluation Results 66
V Reparo: A Fast RAID Recovery Scheme for Ultra- Large SSDs 70
5.1 SSD Failures: Causes and Characteristics 70
5.1.1 SSD Failure Types 70
5.1.2 SSD Failure Characteristics 72
5.2 Impact of UL SSDs on RAID Reliability 74
5.3 RAID Recovery using Reparo 77
5.3.1 Overview of Reparo 77
5.4 Cooperative Die Recovery 82
5.4.1 Identifier: Parallel Search of Failed LBAs 82
5.4.2 Handler: Per-Core Space Utilization Adjustment 83
5.5 Identifier Acceleration Using P2L Mapping Information 89
5.5.1 Page-level P2L Entrustment to Neighboring Die 90
5.5.2 Block-level P2L Entrustment to Neighboring Die 92
5.5.3 Additional Considerations for P2L Entrustment 94
5.6 Experimental Results 95
5.6.1 Experimental Settings 95
5.6.2 Experimental Results 97
VI Conclusions 109
6.1 Summary 109
6.2 Future Work 111
6.2.1 Optimization with Accurate WAF Prediction 111
6.2.2 Maximizing Copyback Threshold 111
6.2.3 Pre-failure Detection 112λ°
Self-Learning Hot Data Prediction: Where Echo State Network Meets NAND Flash Memories
Β© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Well understanding the access behavior of hot data is significant for NAND flash memory due to its crucial impact on the efficiency of garbage collection (GC) and wear leveling (WL), which respectively dominate the performance and life span of SSD. Generally, both GC and WL rely greatly on the recognition accuracy of hot data identification (HDI). However, in this paper, the first time we propose a novel concept of hot data prediction (HDP), where the conventional HDI becomes unnecessary. First, we develop a hybrid optimized echo state network (HOESN), where sufficiently unbiased and continuously shrunk output weights are learnt by a sparse regression based on L2 and L1/2 regularization. Second, quantum-behaved particle swarm optimization (QPSO) is employed to compute reservoir parameters (i.e., global scaling factor, reservoir size, scaling coefficient and sparsity degree) for further improving prediction accuracy and reliability. Third, in the test on a chaotic benchmark (Rossler), the HOESN performs better than those of six recent state-of-the-art methods. Finally, simulation results about six typical metrics tested on five real disk workloads and on-chip experiment outcomes verified from an actual SSD prototype indicate that our HOESN-based HDP can reliably promote the access performance and endurance of NAND flash memories.Peer reviewe
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