5 research outputs found
Efficient Exploration of Bus-Based System-on-Chip Architectures
Separation between computation and communication
in system design allows system designers to explore the communication
architecture independently after component selection and
mapping decision is made. In this paper, we present an iterative
two-step exploration methodology for bus-based on-chip communication
architecture for multitask applications. We assume that
the memory traces from the processing components are given.
The proposed methodology uses a static performance estimation
technique extended for multitask applications to reduce the design
space quickly and drastically and applies a trace-driven simulation
to the reduced set of design candidates for accurate performance
estimation. For the case that local memory traffics as well as
shared memory traffics are involved in bus contention, memory
allocation is considered as an important axis of the design space
in our technique. Experimental results show that the proposed
methodology achieves significant performance gain by optimizing
on-chip communication only, up to almost 100% compared with
an initial single shared bus architecture, in both two real-life
examples, a four-Channel digital video recorder and an equalizer
for OFDM DVB-T receiverThis work
was supported by the National Research Laboratory Program under Grant
M1-0104-00-0015 and the IT Leading Research and Development Support
Project funded by Korean MIC
Schedule-Aware Performance Estimation of Communication Architecture for Efficient Design Space Exploration
In this paper,we are concerned about performance estimation
of bus-based communication architectures assuming that
task partitioning and scheduling on processing elements are already
determined. Since communication overhead is dynamic and
unpredictable due to bus contention, a simulation-based approach
seems inevitable for accurate performance estimation. However,
it is too time-consuming to be used for exploring the wide design
space of bus architectures. We propose a static performance-estimation
technique based on a queueing analysis assuming that the
memory traces and the task schedule information are given. We
use this static estimation technique as the first step in our design
space exploration framework to prune the design space drastically
before applying a simulation-based approach to the reduced design
space. Experimental results show that the proposed technique
is several orders of magnitude faster than a trace-driven simulation
while keeping the estimation error within 10% consistently in
various communication architecture configurations.This work was supported by the National Research Laboratory under Program
M1-0104-00-0015, Brain Korea 21 Project, and the IT-SoC project. ICT
at Seoul National University provided research facilities for this study
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC