1,437 research outputs found

    Flow conveying and diagnosis with carbon nanotube arrays

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    Dense arrays of aligned carbon nanotubes are designed into strips, nanowicks, as a miniature wicking element for liquid delivery and potential microfluidic chemical analysis devices. Liquid wicks away along the nanowicks spontaneously. This delivery function of nanowicks enables novel fluid transport devices to run without any power input, moving parts or external pump. Flow around the opaque nanotubes can be detected either directly or indirectly. Direct signals of the flow come out of dyed liquid or from the liquid–air interface; indirect signals are detected through observing surface-tension-induced deformation and dislocation of the nanotubes. Here we show that flow progression around and inside nanowicks is sensitive to liquid properties. Different flow progression leaves different traces of liquid. These traces not only allow liquid diagnosis any time after sampling, but also enable analysis of flow at a nanoscale resolution with scanning electron microscopy

    Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies

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    Department of Electrical EngineeringAs the CMOS technologies reach the nanometer regime through aggressive scaling, integrated circuits (ICs) encounter scaling impediments such as short channel effects (SCE) caused by reduced ability of gate control on the channel and line-edge roughness (LER) caused by limits of the photolithography technologies, leading to serious device parameter fluctuations and makes the circuit analysis difficult. In order to overcome scaling issues, multi-gate structures are introduced from the planar MOSFET to increase the gate controllability. The goal of this dissertation is to analyze structural variations induced by manufacturing process in advanced nanoscale devices and to optimize its impacts in terms of the circuit performances. If the structural variability occurs, aside from the endeavor to reduce the variability, the impact must be taken into account at the design level. Current compact model does not have device structural variation model and cannot capture the impact on the performance/power of the circuit. In this research, the impacts of structural variation in advanced nanoscale technology on the circuit level parameters are evaluated and utilized to find the optimal device shape and structure through technology computer-aided-design (TCAD) simulations. The detail description of this dissertation is as follows: Structural variation for nanoscale CMOS devices is investigated to extend the analysis approach to multi-gate devices. Simple and accurate modeling that analyzes non-rectilinear gate (NRG) CMOS transistors with a simplified trapezoidal approximation method is proposed. The electrical characteristics of the NRG gate, caused by LER, are approximated by a trapezoidal shape. The approximation is acquired by the length of the longest slice, the length of the smallest slice, and the weighting factor, instead of taking the summation of all the slices into account. The accuracy can even be improved by adopting the width-location-dependent factor (Weff). The positive effect of diffusion rounding at the transistor source side of CMOS is then discussed. The proposed simple layout method provides boosting the driving strength of logic gates and also saving the leakage power with a minimal area overhead. The method provides up to 13% speed up and also saves up to 10% leakage current in an inverter simulation by exploiting the diffusion rounding phenomena in the transistors. The performance impacts of the trapezoidal fin shape of a double-gate FinFET are then discussed. The impacts are analyzed with TCAD simulations and optimal trapezoidal angle range is proposed. Several performance metrics are evaluated to investigate the impact of the trapezoidal fin shape on the circuit operation. The simulations show that the driving capability improves, and the gate capacitance increases as the bottom fin width of the trapezoidal fin increases. The fan-out 4 (FO4) inverter and ring-oscillator (RO) delay results indicate that careful optimization of the trapezoidal angle can increase the speed of the circuit because the ratios of the current and capacitance have different impacts depending on the trapezoidal angle. Last but not least, the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using device simulations are also investigated in this work. The DGAA FET, a kind of nanotube field-effect transistor (NTFET), can solve the problem of loss of gate controllability of the channel and provide improved short-channel behavior. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, this work proposes the n/p DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional GAA inverter structure. In the optimum structure, 27% propagation delay and 15% leakage power improvement can be achieved. Analysis and optimization for device-level variability are critical in integrated circuit designs of advanced technology nodes. Thus, the proposed methods in this dissertation will be helpful for understanding the relationship between device variability and circuit performance. The research for advanced nanoscale technologies through intensive TCAD simulations, such as FinFET and GAA, suggests the optimal device shape and structure. The results provide a possible solution to design high performance and low power circuits with minimal design overhead.ope

    Helium Ion Microscopy

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    Helium Ion Microcopy (HIM) based on Gas Field Ion Sources (GFIS) represents a new ultra high resolution microscopy and nano-fabrication technique. It is an enabling technology that not only provides imagery of conducting as well as uncoated insulating nano-structures but also allows to create these features. The latter can be achieved using resists or material removal due to sputtering. The close to free-form sculpting of structures over several length scales has been made possible by the extension of the method to other gases such as Neon. A brief introduction of the underlying physics as well as a broad review of the applicability of the method is presented in this review.Comment: Revised versio

    Design, development and simulation of sub-lithographic process for patterning nm scale features

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    The ability to create sub-lithographic nm-scale features without the need of high-end lithography tools will create new opportunities for the electronics industry. Most current technologies are lithography dependent and inherit associated CD variations. The mainstay of this work is mathematical modeling, simulation and verification of a revolutionary void transfer process for patterning nm scale features originally introduced by Breitwisch et al. at IBM. The technique studied involves intentional creation of voids using a conformal chemical vapor deposition (CVD) followed by controlled etch-back to form nanoscale pores. This method provides features that are independent of lithographically defined parent holes and exhibit lower critical dimension (CD) variations. It offers efficient low thermal budget and backend process compatible integration scheme that requires just one additional mask level. To the best of author\u27s knowledge no simulation study of the void transfer process has been reported in the literature so far. Thus, this project initiated scores of `firsts\u27 towards the development of a reliable nano-patterning technique and a robust process infrastructure for future projects at RIT. The pores with diameter of 130 nm were obtained i.e. an impressive ~7X reduction from lithographically defined hole of 714 nm using conventional i-line lithography. Critical parameters affecting the void formation and the final pore size have been identified and modeled. Simulation of the void transfer process has been investigated using plasma etch module of `Elite\u27 by Silvaco that employs 2-D Monte Carlo ion transport modeling. The results of this investigation show that the geometrical design parameters can be coupled with the plasma process simulations to develop an efficient module for the void transfer process

    Performance-Based Optical Proximity Correction

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    Ph.DDOCTOR OF PHILOSOPH
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