Millimeter-wave Wireless LAN and its Extension toward 5G Heterogeneous Networks

Millimeter-wave (mmw) frequency bands, especially 60 GHz unlicensed band, are considered as a promising solution for gigabit short range wireless communication systems. IEEE standard 802.11ad, also known as WiGig, is standardized for the usage of the 60 GHz unlicensed band for wireless local area networks (WLANs). By using this mmw WLAN, multi-Gbps rate can be achieved to support bandwidth-intensive multimedia applications. Exhaustive search along with beamforming (BF) is usually used to overcome 60 GHz channel propagation loss and accomplish data transmissions in such mmw WLANs. Because of its short range transmission with a high susceptibility to path blocking, multiple number of mmw access points (APs) should be used to fully cover a typical target environment for future high capacity multi-Gbps WLANs. Therefore, coordination among mmw APs is highly needed to overcome packet collisions resulting from un-coordinated exhaustive search BF and to increase the total capacity of mmw WLANs. In this paper, we firstly give the current status of mmw WLANs with our developed WiGig AP prototype. Then, we highlight the great need for coordinated transmissions among mmw APs as a key enabler for future high capacity mmw WLANs. Two different types of coordinated mmw WLAN architecture are introduced. One is the distributed antenna type architecture to realize centralized coordination, while the other is an autonomous coordination with the assistance of legacy Wi-Fi signaling. Moreover, two heterogeneous network (HetNet) architectures are also introduced to efficiently extend the coordinated mmw WLANs to be used for future 5th Generation (5G) cellular networks.Comment: 18 pages, 24 figures, accepted, invited paper

Miniaturized Resonator and Bandpass Filter for Silicon-Based Monolithic Microwave and Millimeter-Wave Integrated Circuits

© 2018 IEEE. © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.This paper introduces a unique approach for the implementation of a miniaturized on-chip resonator and its application for the first-order bandpass filter (BPF) design. This approach utilizes a combination of a broadside-coupling technique and a split-ring structure. To fully understand the principle behind it, simplified LC equivalent-circuit models are provided. By analyzing these models, guidelines for implementation of an ultra-compact resonator and a BPF are given. To further demonstrate the feasibility of using this approach in practice, both the implemented resonator and the filter are fabricated in a standard 0.13-μm (Bi)-CMOS technology. The measured results show that the resonator can generate a resonance at 66.75 GHz, while the BPF has a center frequency at 40 GHz and an insertion loss of 1.7 dB. The chip size of both the resonator and the BPF, excluding the pads, is only 0.012mm 2 (0.08 × 0.144 mm 2).Peer reviewe

Enhancing Digital Controllability in Wideband RF Transceiver Front-Ends for FTTx Applications

Enhancing the digital controllability of wideband RF transceiver front-ends helps in widening the range of operating conditions and applications in which such systems can be employed. Technology limitations and design challenges often constrain the extensive adoption of digital controllability in RF front-ends. This work focuses on three major aspects associated with the design and implementation of a digitally controllable RF transceiver front-end for enhanced digital control. Firstly, the influence of the choice of semiconductor technology for a system-on-chip integration of digital gain control circuits are investigated. The digital control of gain is achieved by utilizing step attenuators that consist of cascaded switched attenuation stages. A design methodology is presented to evaluate the influence of the chosen technology on the performance of the three conventionally used switched attenuator topologies for desired attenuation levels, and the constraints that the technology suitable for high amplification places on the attenuator performance are examined. Secondly, a novel approach to the integrated implementation of gain slope equalization is presented, and the suitability of the proposed approach for integration within the RF front-end is verified. Thirdly, a sensitivity-aware implementation of a peak power detector is presented. The increased employment of digital gain control also increases the requirements on the sensitivity of the power detector employed for adaptive power and gain control. The design, implementation, and measurement results of a state-of-the-art wideband power detector with high sensitivity and large dynamic range are presented. The design is optimized to provide a large offset cancellation range, and the influence of offset cancellation circuits on the sensitivity of the power detector is studied. Moreover, design considerations for high sensitivity performance of the power detector are investigated, and the noise contributions from individual sub-circuits are evaluated. Finally, a wideband RF transceiver front-end is realized using a commercially available SiGe BiCMOS technology to demonstrate the enhancements in the digital controllability of the system. The RF front-end has a bandwidth of 500 MHz to 2.5 GHz, an input dynamic range of 20 dB, a digital gain control range larger than 30 dB, a digital gain slope equalization range from 1.49 dB/GHz to 3.78 dB/GHz, and employs a power detector with a sensitivity of -56 dBm and dynamic range of 64 dB. The digital control in the RF front-end is implemented using an on-chip serial-parallel-interface (SPI) that is controlled by an external micro-controller. A prototype implementation of the RF front-end system is presented as part of an RFIC intended for use in optical transceiver modules for fiber-to-the-x applications

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

The availability of quantum microprocessors is mandatory, to efficiently run those quantum al-gorithms promising a radical leap forward in computation capability. Silicon-based nanostruc-tured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthe-size control signals for spintronic qubits. In a quantum microprocessor, these circuits should op-erate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been sys-tematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physi-cal models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guide-lines for the VCO/FD interface, useful in the absence of cryogenic DKs

A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

Capacitive coupled RFID tag using a new dielectric droplet encapsulation approach

Radio frequency identification (RFID) is a well-known and fast-growing technology used to identify people, animals and products. RFID tags are used to replace bar codes in a wide range of applications, to mention just a few, retail, transportation, logistics and healthcare. The two main driving aspects for most of research and development projects concerning RFID tags are the reduction of assembly costs and the downsizing of microchips. In that respect and considering an Industry 4.0 scenario, the study of a new assembly approach for passive and high frequency RFID tags has been proposed and studied in this thesis. In this new approach, which is based on the inkjet printing technology, a specifically designed radio frequency integrated circuit (RFIC) will be delivered, inside a liquid dielectric droplet, onto the antenna and no longer placed and oriented precisely as it happens nowadays with pick-and-place and flip chip machines. After a landing phase, the liquid droplet (with the encapsulated chip) will self-aligns with respect to the contact thanks to capillary forces driven by specifically designed wetting conditions on the substrate of the antenna. Finally, with few additional steps, the complete RFID tag is created. This research project brings to light a considerable simplification and a very high potential of parallelization, compatible with large volume manufacturing methods, in comparison to nowadays existing technologies. This may substantially drive down the fabrication costs. An in-depth analysis of electrical performances have been carefully undertaken and compliance with the ISO/IEC 144443 standard has been verified. Mathematical models have been developed showing fundamental limits for the maximum tag reading range and power requirements of the RFID reader

Analysis and Design of Silicon based Integrated Circuits for Radio Frequency Identification and Ranging Systems at 24GHz and 60GHz Frequency Bands

This scientific research work presents the analysis and design of radio frequency (RF) integrated circuits (ICs) designed for two cooperative RF identification (RFID) proof of concept systems. The first system concept is based on localizable and sensor-enabled superregenerative transponders (SRTs) interrogated using a 24GHz linear frequency modulated continuous wave (LFMCW) secondary radar. The second system concept focuses on low power components for a 60GHz continuous wave (CW) integrated single antenna frontend for interrogating close range passive backscatter transponders (PBTs). In the 24GHz localizable SRT based system, a LFMCW interrogating radar sends a RF chirp signal to interrogate SRTs based on custom superregenerative amplifier (SRA) ICs. The SRTs receive the chirp and transmit it back with phase coherent amplification. The distance to the SRTs are then estimated using the round trip time of flight method. Joint data transfer from the SRT to the interrogator is enabled by a novel SRA quench frequency shift keying (SQ-FSK) based low data rate simplex communication. The SRTs are also designed to be roll invariant using bandwidth enhanced microstrip patch antennas. Theoretical analysis is done to derive expressions as a function of system parameters including the minimum SRA gain required for attaining a defined range and equations for the maximum number of symbols that can be transmitted in data transfer mode. Analysis of the dependency of quench pulse characteristics during data transfer shows that the duty cycle has to be varied while keeping the on-time constant to reduce ranging errors. Also the worsening of ranging precision at longer distances is predicted based on the non-idealities resulting from LFMCWchirp quantization due to SRT characteristics and is corroborated by system level measurements. In order to prove the system concept and study the semiconductor technology dependent factors, variants of 24GHz SRA ICs are designed in a 130nm silicon germanium (SiGe) bipolar complementary metal oxide technology (BiCMOS) and a partially depleted silicon on insulator (SOI) technology. Among the SRA ICs designed, the SiGe-BiCMOS ICs feature a novel quench pulse shaping concept to simultaneously improve the output power and minimum detectable input power. A direct antenna drive SRA IC based on a novel stacked transistor cross-coupled oscillator topology employing this concept exhibit one of the best reported combinations of minimum detected input power level of −100 dBm and output power level of 5.6 dBm, post wirebonding. The SiGe stacked transistor with base feedback capacitance topology employed in this design is analyzed to derive parameters including the SRA loop gain for design optimization. Other theoretical contributions include the analysis of the novel integrated quench pulse shaping circuit and formulas derived for output voltage swing taking bondwire losses into account. Another SiGe design variant is the buffered antenna drive SRA IC having a measured minimum detected input power level better than −80 dBm, and an output power level greater than 3.2 dBm after wirebonding. The two inputs and outputs of this IC also enables the design of roll invariant SRTs. Laboratory based ranging experiments done to test the concepts and theoretical considerations show a maximum measured distance of 77m while transferring data at the rate of 0.5 symbols per second using SQ-FSK. For distances less than 10m, the characterized accuracy is better than 11 cm and the precision is better than 2.4 cm. The combination of the maximum range, precision and accuracy are one of the best reported among similar works in literature to the author’s knowledge. In the 60GHz close range CW interrogator based system, the RF frontend transmits a continuous wave signal through the transmit path of a quasi circulator (QC) interfaced to an antenna to interrogate a PBT. The backscatter is received using the same antenna interfaced to the QC. The received signal is then amplified and downconverted for further processing. To prove this concept, two optimized QC ICs and a downconversion mixer IC are designed in a 22nm fully depleted SOI technology. The first QC is the transmission lines based QC which consumes a power of 5.4mW, operates at a frequency range from 56GHz to 64GHz and occupies an area of 0.49mm2. The transmit path loss is 5.7 dB, receive path gain is 2 dB and the tunable transmit path to receive path isolation is between 20 dB and 32 dB. The second QC is based on lumped elements, and operates in a relatively narrow bandwidth from 59.6GHz to 61.5GHz, has a gain of 8.5 dB and provides a tunable isolation better than 20 dB between the transmit and receive paths. This QC design also occupies a small area of 0.34mm² while consuming 13.2mW power. The downconversion is realized using a novel folded switching stage down conversion mixer (FSSDM) topology optimized to achieve one of the best reported combination of maximum voltage conversion gain of 21.5 dB, a factor of 2.5 higher than reported state-of-the-art results, and low power consumption of 5.25mW. The design also employs a unique back-gate tunable intermediate frequency output stage using which a gain tuning range of 5.5 dB is attained. Theoretical analysis of the FSSDM topology is performed and equations for the RF input stage transconductance, bandwidth, voltage conversion gain and gain tuning are derived. A feasibility study for the components of the 60GHz integrated single antenna interrogator frontend is also performed using PBTs to prove the system design concept.:1 Introduction 1 1.1 Motivation and Related Work . . . . . . . . . . . . . . . . . . . . . 1 1.2 Scope and Functional Specifications . . . . . . . . . . . . . . . . . 4 1.3 Objectives and Structure . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Features and Fundamentals of RFIDs and Superregenerative Amplifiers 9 2.1 RFID Transponder Technology . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Chipless RFID Transponders . . . . . . . . . . . . . . . . . 10 2.1.2 Semiconductor based RFID Transponders . . . . . . . . . . 11 2.1.2.1 Passive Transponders . . . . . . . . . . . . . . . . 11 2.1.2.2 Active Transponders . . . . . . . . . . . . . . . . . 13 2.2 RFID Interrogator Architectures . . . . . . . . . . . . . . . . . . . 18 2.2.1 Interferometer based Interrogator . . . . . . . . . . . . . . . 19 2.2.2 Ultra-wideband Interrogator . . . . . . . . . . . . . . . . . . 20 2.2.3 Continuous Wave Interrogators . . . . . . . . . . . . . . . . 21 2.3 Coupling Dependent Range and Operating Frequencies . . . . . . . 25 2.4 RFID Ranging Techniques . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.0.1 Received Signal Strength based Ranging . . . . . 28 2.4.0.2 Phase based Ranging . . . . . . . . . . . . . . . . 30 2.4.0.3 Time based Ranging . . . . . . . . . . . . . . . . . 30 2.5 Architecture Selection for Proof of Concept Systems . . . . . . . . 32 2.6 Superregenerative Amplifier (SRA) . . . . . . . . . . . . . . . . . . 35 2.6.1 Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 42 2.6.3 Frequency Domain Characteristics . . . . . . . . . . . . . . 45 2.7 Semiconductor Technologies for RFIC Design . . . . . . . . . . . . 48 2.7.1 Silicon Germanium BiCMOS . . . . . . . . . . . . . . . . . 48 2.7.2 Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . 48 3 24GHz Superregenerative Transponder based Identification and Rang- ing System 51 3.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.1 SRT Identification and Ranging . . . . . . . . . . . . . . . . 51 3.1.2 Power Link Analysis . . . . . . . . . . . . . . . . . . . . . . 55 3.1.3 Non-idealities . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.4 SRA Quench Frequency Shift Keying for data transfer . . . 61 3.1.5 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.1 Low Power Direct Antenna Drive CMOS SRA IC . . . . . . 66 3.2.1.1 Circuit analysis and design . . . . . . . . . . . . . 66 3.2.1.2 Characterization . . . . . . . . . . . . . . . . . . . 69 3.2.2 Direct Antenna Drive SiGe SRA ICs . . . . . . . . . . . . . 71 3.2.2.1 Stacked Transistor Cross-coupled Quenchable Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.2.1.1 Resonator . . . . . . . . . . . . . . . . . . 72 3.2.2.1.2 Output Network . . . . . . . . . . . . . . 75 3.2.2.1.3 Stacked Transistor Cross-coupled Pair and Loop Gain . . . . . . . . . . . . . . . . . 77 3.2.2.2 Quench Waveform Design . . . . . . . . . . . . . . 85 3.2.2.3 Characterization . . . . . . . . . . . . . . . . . . . 89 3.2.3 Antenna Diversity SiGe SRA IC with Integrated Quench Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.2.3.1 Circuit Analysis and Design . . . . . . . . . . . . 91 3.2.3.1.1 Crosscoupled Pair and Sampling Current 94 3.2.3.1.2 Common Base Input Stage . . . . . . . . 95 3.2.3.1.3 Cascode Output Stage . . . . . . . . . . . 96 3.2.3.1.4 Quench Pulse Shaping Circuit . . . . . . 96 3.2.3.1.5 Power Gain . . . . . . . . . . . . . . . . . 99 3.2.3.2 Characterization . . . . . . . . . . . . . . . . . . . 102 3.2.4 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 103 3.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 106 3.3.1 Superregenerative Transponders . . . . . . . . . . . . . . . 106 3.3.1.1 Bandwidth Enhanced Microstrip Patch Antennas 108 3.3.2 FMCW Radar Interrogator . . . . . . . . . . . . . . . . . . 114 3.3.3 Chirp Z-transform Based Data Analysis . . . . . . . . . . . 116 4 60GHz Single Antenna RFID Interrogator based Identification System 121 4.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1 Quasi-circulator ICs . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1.1 Transmission Lines based Quasi-Circulator IC . . 126 4.2.1.2 Lumped Elements WPD based Quasi-Circulator . 130 4.2.1.3 Characterization . . . . . . . . . . . . . . . . . . . 134 4.2.1.4 Knowledge Gained . . . . . . . . . . . . . . . . . . 135 4.2.2 Folded Switching Stage Downconversion Mixer IC . . . . . 138 4.2.2.1 FSSDM Circuit Design . . . . . . . . . . . . . . . 138 4.2.2.2 Cascode Transconductance Stage . . . . . . . . . . 138 4.2.2.3 Folded Switching Stage with LC DC Feed . . . . . 142 4.2.2.4 LO Balun . . . . . . . . . . . . . . . . . . . . . . . 145 4.2.2.5 Backgate Tunable IF Stage and Offset Correction 146 4.2.2.6 Voltage Conversion Gain . . . . . . . . . . . . . . 147 4.2.2.7 Characterization . . . . . . . . . . . . . . . . . . . 150 4.2.2.8 Knowledge Gained . . . . . . . . . . . . . . . . . . 151 4.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 154 5 Experimental Tests 157 5.1 24GHz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.1.1 Ranging Experiments . . . . . . . . . . . . . . . . . . . . . 157 5.1.2 Roll Invariance Experiments . . . . . . . . . . . . . . . . . . 158 5.1.3 Joint Ranging and Data Transfer Experiments . . . . . . . 158 5.2 60GHz System Detection Experiments . . . . . . . . . . . . . . . . 165 6 Summary and Future Work 167 Appendices 171 A Derivation of Parameters for CB Amplifier with Base Feedback Capac- itance 173 B Definitions 177 C 24GHz Experiment Setups 179 D 60 GHz Experiment Setups 183 References 185 List of Original Publications 203 List of Abbreviations 207 List of Symbols 213 List of Figures 215 List of Tables 223 Curriculum Vitae 22

Development of interconnections for mm-wave antenna module package

Abstract. The increase in mobile network data usage has led to interests in mm-wave frequencies (for example 26.5–29.5 GHz) on becoming fifth generation (5G) networks in addition to previously used sub-6 GHz frequencies. The advantage of mm-wave frequencies is larger bandwidth, leading to larger throughput with a tradeoff of smaller coverage due to shorter wavelength. The coverage issue can be compensated by using antenna arrays instead of one antenna. There have been some studies about stacking antenna module package vertically on motherboard, and in more advanced approach, the RFIC is integrated into the bottom of the antenna module package. This thesis concentrates on developing the interconnection between two PWBs on mm-wave frequency (26.5–29.5 GHz) between the antenna module and motherboard. More accurately, creating interconnection around via structure, carrying RF-signal from antenna module to motherboard by applying vertical stacking. This method may reduce the overall price of the system, while increasing the level of integration in the system. The overall aim of this thesis was to provide a functional and optimized interconnection method with measurement results and limitations of Nokia Factory. The interconnection can be created by using electromagnetic coupling or galvanic connection. The galvanic connection was chosen for many reasons and different interconnection methods applying galvanic connection were introduced. These methods include LGA and BGA soldering, traditional RF-connector and antenna array connector with 16-ports. After considering the options and Nokia Factory limitations, the most suitable interconnection method turned out to be LGA soldering. The research work includes partial design of antenna module and motherboard, and the optimization for connection. Prototypes were created based on the design, and the measurement results and conclusions of interconnection functionality were provided as well. Six prototypes were made, from which prototypes 3–6 were functional in terms of solder height. The measurement results show that there was variation in matching between different prototypes and between simulation and measurement results. By doing x-ray and failure analysis, a few reasons were found to explain the variation. One reason can be found from voids in signal soldering, which widens the soldering horizontally, leading to decreased matching due to changed solder diameter and asymmetric grounding. However, by utilizing the solder bumping method, the appearance and diameter of voids can be minimized. The conclusion with prototypes was that the system functions well, but improvements are recommended, and simulations should be re-done with modifications from failure analysis. Overall, the aim of the thesis was reached.Antennimoduulipaketin liitäntöjen kehittäminen millimetriaalto taajuuksille. Tiivistelmä. Datankäytön jatkuvan kasvun takia viidennen sukupolven (5G) matkapuhelinteknologian kehitys on keskittynyt aiemmin käytettyjen alle 6 GHz taajuuksien lisäksi uusille, korkeammille, millimetriaaltojen (esim. 26.5–29.5 GHz) taajuuskaistalle. Korkeammat taajuudet tarjoavat mahdollisuuden käyttää suurempia kaistanleveyksiä kasvattaen läpikulkevan datan määrää, mutta sen hintana on signaalin kantomatkan pienentyminen aallonpituuden pienentymisen takia. Kantomatkan lyhenemistä voidaan kuitenkin kompensoida käyttämällä antenniryhmiä yksittäisten antennien asemasta. Antenniryhmien integroinnista systeemiin on tehty erilaisia tutkimuksia, joita ovat esimerkiksi vertikaalinen pinoaminen, jossa antennilevy juotetaan toiselle piirilevylle. Edistyksellisemmässä versiossa kyseisen antennilevyn pohjaan on liitetty RFIC piiri. Tässä diplomityössä tutkittiin kahden piirilevyn välistä liityntäkohtaa vertikaalisella pinoamisella. Liityntäkohta kuljettaa millimetriaaltotaajuista RF-signaalia (26.5–29.5 GHz) antennilevyltä äitilevylle. Kyseisellä rakenteella voidaan saada pienennettyä mahdollisen tuotteen kustannuksia, samalla pienentäen myös sen fyysistä kokoa. Työn tarkoituksena on tarjota Nokialle valmiiksi optimoitu liitäntäratkaisu mittaustuloksineen ja tuotannon rajoitteineen dokumentoituna. Tutkittu liityntäkohta voidaan muodostaa sähkömagneettisella kytkeytymisellä tai galvaanisesti, joista jälkimmäinen on huomattavasti järkevämpi ja tässä työssä on esitetty sille erilaisia vaihtoehtoja, joita on vertailtu toisiinsa. Näihin vaihtoehtoihin sisältyy koneellinen juottaminen LGA tai BGA tavalla, RF-liittimien käyttö ja antenniryhmää varten kehitetty 16 porttinen liitin. Kyseisistä liitäntä vaihtoehdoista parhaaksi ja soveltuvimmaksi osoittautui LGA juotos. Tutkimustyö sisältää antennilevyn ja äitilevyn osittaisen suunnittelun ja optimoinnin, ja sen perusteella tehdyn prototyypin, mittaustulokset ja päätelmät liitynnän toimivuudesta. Prototyyppejä tehtiin kaikkiaan kuusi, joista viimeiset 3–6 olivat onnistuneita juotospaksuuden perusteella. Mittausten perusteella sovituksessa on paljon vaihtelua, jolle löydettiin muutamia syitä röntgen tarkastuksessa ja virheanalyysissa. Näihin syihin sisältyy juotoksesta löytyneet kaasukuplat, jotka johtavat juotoksen laajenemiseen horisontaalisesti, mikä taas heikentää maadoitusta ja täten sovitusta. Juotoksen kaasukuplat voidaan kuitenkin välttää niin kutsutulla juotoksen pallottamisella (Engl. Solder Bumping), jossa kaasukuplia ilmeni huomattavasti vähemmän ja ne olivat pienempiä. Lopputulemana todettiin, että työ on onnistunnut ja prototyyppi on toimiva, mutta tarjotut kehitysideat kannattaa huomioida mahdollisessa jatkokehityksessä ja simuloinnit tulisi tehdä uudelleen virheanalyysistä saaduilla arvoilla ja tiedoilla