Adaptive differential amplitude pulse-position modulation technique (DAPPM) using fuzzy logic for optical wireless communication channels

In the past few years, people have become increasingly demanding for high transmission rate, using high-speed data transfer rate, the number of user increased every year, therefore the high-speed optical wireless communication link have become more popular. Optical wireless communication has the potential for extremely high data rates of up to tens of Gigabits per second (Gb/s). An optical wireless channel is usually a non-directed link which can be categorized as either line-of-sight (LOS) or diffuses. Modulation techniques have attracted increasing attention in optical wireless communication, therefore in this project; a hybrid modulation technique named Differential Amplitude Pulse-Position Modulation (DAPPM) is proposed to improve the channel immunity by utilizing optimized modulation to channel. The average symbol length, unit transmission rate, channel capacity, peak-to-average power ratio (PAPR), transmission capacity, bandwidth requirement and power requirement of the DAPPM were determined and compared with other modulation schemes such as On-Off Key (OOK), Pulse-Amplitude Modulation (PAM), Pulse-Position Modulation (PPM), Differential Pulse-Position Modulation (DPPM), and Multilevel Digital Pulse Interval Modulation (MDPIM). Simulation result shows that DAPPM gives better bandwidth and power efficiency depending on the number of amplitude level (A) and the maximum length (L) of a symbol. In addition, the fuzzy logic module is developed to assist the adaptation process of differential amplitude pulse-position modulation. Mamdani fuzzy logic method is used in which the decisions made by the system will be approaching to what would be decided by the user in the real world

Variability-Aware Design of Subthreshold Devices

Over the last 10 years, digital subthreshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the priority. Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this thesis, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. The goal of this technique is to construct and inscribe a maximum yield cube in the 3-D feasible region composed of oxide thickness, gate length, and channel doping concentration. The center of this cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimized for subthreshold operation in terms of the desired total leakage current and intrinsic delay bounds. To develop the concept of the technique, sample devices are designed for 90nm and 65nm technologies. Monte Carlo simulations verify the accuracy of the technique for meeting power and delay constraints under technology-specific variances of the design parameters of the device

Interconnect yield analysis and fault tolerance for field programmable gate arrays

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Integrated circuit outlier identification by multiple parameter correlation

Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed