랜덤 불연속 도펀트에 의한 전류 산포 TCAD 시뮬레이션에 적합한 이동도 모델

학위논문 (석사)-- 서울대학교 대학원 공과대학 전기·정보공학부, 2017. 8. 박영준.In order to investigate the influence of drive current fluctuation by random discrete dopant (RDD) in the source/drain region using drift-diffusion (DD) solver, a new mobility model with mobility doping profile is proposed considering the nonlocal effect of the Coulomb scattering. The similar approach proposed by Sano is used to create a new impurity profile and introduce the charge smoothing parameter (rcs) to match with the experimental values for the mobility vs. doping concentration. Smoothed doping profile with rcs is used only for the doping dependent mobility calculation and the carrier localization by RDD is resolved using density gradient (DG) method. In summary, two input doping profiles is used to TCAD simulationone for the impurity mobility and the other is the real RDD profile for the Poisson equation. It is interesting to notice that our mobility model for the RDD effect may capture some of the screening related physics even though rcs is not exactly same as the screening length in the Brooks-Herring model. In addition to the Coulomb mobility due to the RDD effect, mobility degradation by the normal field to the gate and parallel field should be considered. In particular, degradation of the mobility due to the normal and parallel fields in the lightly doped (RDD) in the source and drain regions gives additional limitation in the driving current of the DRAM cell transistors. A strategy for the field dependent mobility models is rather empirical. The Lombardi model for normal field dependence and the extended Canali model for high field dependence with fitting parameters in the models were employed. The proposed model has been applied to the DRAM cell transistor of the 20 nm technology generation. The RDD effect in the drain region of the cell transistor alone gives relative standard variation in the driving current of ~3.1%. In this thesis, the simple and efficient doping dependent mobility model is proposed. This model is expected to provide a clue of the variation reduction strategy together with the mobility boosting technique based on the material and device structure.Chapter 1. Introduction 1 1.1. Motivation 1 1.3. Outline of Thesis 5 Chapter 2. Theoretical Background 6 2.1. Density gradient (DG) method 6 2.2. Mobility model 8 Chapter 3. Simulation Methodology 11 3.1. Sequence of mobility model development 11 3.2. Concept of the mobility doping 14 3.3. The charge smoothing radius (rcs)in themobility doping 17 3.4. Normal and parallel fields dependent mobility 22 Chapter 4. Application to DRAM cell transistor 27 4.1. DRAM cell structure 27 4.2. Impact of RDD on drive current variation 29 Chapter 5. Conclusion 31 Bibliography 32 Abstract in Korean 36Maste

VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY

This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM)

A Rigorous Simulation Based Study of Gate Misalignment Effects in Gate Engineered Double-Gate (DG) MOSFETs

In this work, a numerical simulation based study on the effects of gate misalignment between the front and the back gate for gate engineered double-gate (DG) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) has been presented. A comparative study of electrical characteristics and its effects on device performance between single material double gate (SMDG), double material double gate (DMDG) and triple material double gate (TMDG) MOSFETs have been investigated qualitatively. Both source side misalignment (SSM) and drain side misalignment (DSM) of different lengths in the back gate have been considered to investigate the effects of gate misalignment on device performance. In this context, an extensive simulation has been performed by a commercially available two-dimensional (2D) device simulator (ATLASTM, SILVACO Int.) to figure out the impacts of misalignment on device characteristics like surface potential, threshold voltage, drain-induced-barrier lowering (DIBL), subthreshold swing, subthreshold current, maximum drain current, transconductance and output conductance

Fault- and Yield-Aware On-Chip Memory Design and Management

Ever decreasing device size causes more frequent hard faults, which becomes a serious burden to processor design and yield management. This problem is particularly pronounced in the on-chip memory which consumes up to 70% of a processor' s total chip area. Traditional circuit-level techniques, such as redundancy and error correction code, become less effective in error-prevalent environments because of their large area overhead. In this work, we suggest an architectural solution to building reliable on-chip memory in the future processor environment. Our approaches have two parts, a design framework and architectural techniques for on-chip memory structures. Our design framework provides important architectural evaluation metrics such as yield, area, and performance based on low level defects and process variations parameters. Processor architects can quickly evaluate their designs' characteristics in terms of yield, area, and performance. With the framework, we develop architectural yield enhancement solutions for on-chip memory structures including L1 cache, L2 cache and directory memory. Our proposed solutions greatly improve yield with negligible area and performance overhead. Furthermore, we develop a decoupled yield model of compute cores and L2 caches in CMPs, which show that there will be many more L2 caches than compute cores in a chip. We propose efficient utilization techniques for excess caches. Evaluation results show that excess caches significantly improve overall performance of CMPs

Low-Power Soft-Error-Robust Embedded SRAM

Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit can always recover from such errors as the underlying semiconductor material is not damaged and hence, they are called soft errors. In nanometer technologies, the reduced node capacitance and supply voltage coupled with high packing density and lack of masking mechanisms are primarily responsible for the increased susceptibility of SRAMs towards soft errors. Coupled with these are the process variations (effective length, width, and threshold voltage), which are prominent in scaled-down technologies. Typically, SRAM constitutes up to 90% of the die in microprocessors and SoCs (System-on-Chip). Hence, the soft errors in SRAMs pose a potential threat to the reliable operation of the system. In this work, a soft-error-robust eight-transistor SRAM cell (8T) is proposed to establish a balance between low power consumption and soft error robustness. Using metrics like access time, leakage power, and sensitivity to single event transients (SET), the proposed approach is evaluated. For the purpose of analysis and comparisons the results of 8T cell are compared with a standard 6T SRAM cell and the state-of-the-art soft-error-robust SRAM cells. Based on simulation results in a 65-nm commercial CMOS process, the 8T cell demonstrates higher immunity to SETs along with smaller area and comparable leakage power. A 32-kb array of 8T cells was fabricated in silicon. After functional verification of the test chip, a radiation test was conducted to evaluate the soft error robustness. As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers, higher offset voltages lead to an increased likelihood of an incorrect decision. To address this issue, a sense amplifier capable of cancelling the input offset voltage is presented. The simulated and measured results in 180-nm technology show that the sense amplifier is capable of detecting a 4 mV differential input signal under dc and transient conditions. The proposed sense amplifier, when compared with a conventional sense amplifier, has a similar die area and a greatly reduced offset voltage. Additionally, a dual-input sense amplifier architecture is proposed with corroborating silicon results to show that it requires smaller differential input to evaluate correctly.1 yea

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers