Spintronics-based Reconfigurable Ising Model Architecture

Published in the International Symposium On Quality Electronic Design (ISQED), March 2020The Ising model has been explored as a framework for modeling NP-hard problems, with several diverse systems proposed to solve it. The Magnetic Tunnel Junction (MTJ)-based Magnetic RAM is capable of replacing CMOS in memory chips. In this paper, we propose the use of MTJs for representing the units of an Ising model and leveraging its intrinsic physics for finding the ground state of the system through annealing. We design the structure of a basic MTJ-based Ising cell capable of performing the functions essential to an Ising solver. A technique to use the basic Ising cell for scaling to large problems is described. We then go on to propose Ising-FPGA, a parallel and reconfigurable architecture that can be used to map a large class of NP-hard problems, and show how a standard Place and Route tool can be utilized to program the Ising-FPGA. The effects of this hardware platform on our proposed design are characterized and methods to overcome these effects are prescribed. We discuss how two representative NP-hard problems can be mapped to the Ising model. Simulation results show the effectiveness of MTJs as Ising units by producing solutions close/comparable to the optimum, and demonstrate that our design methodology holds the capability to account for the effects of the hardware.This work was supported by the National Science Foundation(NSF) under Grant 164242

Position-Dependent Performance in 5 nm Vertically Stacked Lateral Si Nanowires Transistors

In this work, we investigated the performance of vertically stacked lateral nanowires transistors (NWTs) considering the effects of series resistance. Also, we consider the vertical positions of the lateral nanowires in the stack and diameter variation of the lateral NWTs as new sources of process variability

Variability-Aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors

In this work, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs) considering various sources of statistical variability. Our simulation approach is based on various simulations techniques to capture the complexity in such ultra-scaled device