Factor de olvido matricial para estimación de parámetros en tiempo real en sistemas lineales con parámetros variantes en el tiempo

El estimador Factor de Olvido Matricial (MFF por sus siglas en inglés) es utilizado en sistemas con parámetros variantes en el tiempo del tipo ARMA, estocásticos, lineales, estacionarios y perturbaciones con funciones de distribución normales. Un grave problema se presenta cuando se requiere estimar en Tiempo Real la matriz de parámetros del sistema en estudio; entonces el algoritmo MFF debe cumplir con las características de un Estimador de Parámetros en Tiempo Real EPTR que incluyen: a) Emisión y extracción de respuestas observables respecto a un proceso dinámico real, b) Emisión de respuestas correctas en función a un criterio preestablecido, c) Capacidad de expresarse en forma recursiva, d) Un intervalo de convergencia acotado, e) Manejo de operaciones matriciales y f) Planificabilidad si se implanta en una plataforma de alto nivel.Eje: IV - Workshop de procesamiento distribuido y paraleloRed de Universidades con Carreras en Informática (RedUNCI

Analytical model for staging emergency evacuations

Disaster response in areas of high population density is centered on the efficient evacuation of people and possibly goods. Developing evacuation plans suitable for different levels of urgency based on the intensity of threat is a challenging task. In case of densely populated cities (e.g., New York, Los Angeles), the level of threat is enhanced by the congestion of their transportation systems, and the decision to evacuate a region simultaneously or by dividing it into multiple stages (or zones) affects the required evacuation time and associated delays. The evolution of the traffic conditions on the evacuation route can vary significantly based on the type of evacuation strategy employed (i.e., simultaneous or staged). In this dissertation, mathematical models are developed for estimating evacuation time and delay. Evacuation time is the time for evacuating all vehicles from a designated region, while delay includes queuing and moving delays incurred by evacuees. The base model handles a uniform demand distribution over the evacuation route and deterministic evacuees\u27 behavior. The relationship between delay and evacuation time is investigated, and the impact of a staged versus a simultaneous evacuation is analyzed. A numerical method is adopted to determine the optimal number of staging zones. A sensitivity analysis is conducted of parameters (e.g., demand density, access flow rate, and evacuation route length) affecting evacuation time and delay. To account for the heterogeneous demand distribution over the evacuation region and evacuees\u27 behavioral responses to an evacuation order (e.g., fast, medium, and slow), a more realistic model is developed by enhancing the base model. Based on a numerical searching process, the enhanced model determines the optimal time windows and lengths of individual staged zones dependent on the demand distribution, behavioral response, and evolution of traffic conditions on the evacuation route. The applicability of the model is demonstrated with a numerical example. Results indicate that evacuation time and delay can be significantly reduced if a staged evacuation can be appropriately implemented. Finally, the impact of compliance is investigated. Compliance is defined as the conformity of a staged zone to its demand loading pattern. It is found that the level of compliance and deviation from scheduled access time influence the effectiveness of staging. Further, a method to revise the optimal staging scheme to accommodate the noncompliant demand is illustrated. The models developed in this research can serve as useful tools to provide suitable guidelines for emergency management authorities in making critical decisions during the evacuation process

Applications and implementation of neuro-connectionist architectures.

by H.S. Ng.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references (leaves 91-97).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Introduction --- p.1Chapter 1.2 --- Neuro-connectionist Network --- p.2Chapter 2 --- Related Works --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.1.1 --- Kruskal's Algorithm --- p.5Chapter 2.1.2 --- Prim's algorithm --- p.6Chapter 2.1.3 --- Sollin's algorithm --- p.7Chapter 2.1.4 --- Bellman-Ford algorithm --- p.8Chapter 2.1.5 --- Floyd-Warshall algorithm --- p.9Chapter 3 --- Binary Relation Inference Network and Path Problems --- p.11Chapter 3.1 --- Introduction --- p.11Chapter 3.2 --- Topology --- p.12Chapter 3.3 --- Network structure --- p.13Chapter 3.3.1 --- Single-destination BRIN architecture --- p.14Chapter 3.3.2 --- Comparison between all-pair BRIN and single-destination BRIN --- p.18Chapter 3.4 --- Path Problems and BRIN Solution --- p.18Chapter 3.4.1 --- Minimax path problems --- p.18Chapter 3.4.2 --- BRIN solution --- p.19Chapter 4 --- Analog and Voltage-mode Approach --- p.22Chapter 4.1 --- Introduction --- p.22Chapter 4.2 --- Analog implementation --- p.24Chapter 4.3 --- Voltage-mode approach --- p.26Chapter 4.3.1 --- The site function --- p.26Chapter 4.3.2 --- The unit function --- p.28Chapter 4.3.3 --- The computational unit --- p.28Chapter 4.4 --- Conclusion --- p.29Chapter 5 --- Current-mode Approach --- p.32Chapter 5.1 --- Introduction --- p.32Chapter 5.2 --- Current-mode approach for analog VLSI Implementation --- p.33Chapter 5.2.1 --- Site and Unit output function --- p.33Chapter 5.2.2 --- Computational unit --- p.34Chapter 5.2.3 --- A complete network --- p.35Chapter 5.3 --- Conclusion --- p.37Chapter 6 --- Neural Network Compensation for Optimization Circuit --- p.40Chapter 6.1 --- Introduction --- p.40Chapter 6.2 --- A Neuro-connectionist Architecture for error correction --- p.41Chapter 6.2.1 --- Linear Relationship --- p.42Chapter 6.2.2 --- Output Deviation of Computational Unit --- p.44Chapter 6.3 --- Experimental Results --- p.46Chapter 6.3.1 --- Training Phase --- p.46Chapter 6.3.2 --- Generalization Phase --- p.48Chapter 6.4 --- Conclusion --- p.50Chapter 7 --- Precision-limited Analog Neural Network Compensation --- p.51Chapter 7.1 --- Introduction --- p.51Chapter 7.2 --- Analog Neural Network hardware --- p.53Chapter 7.3 --- Integration of analog neural network compensation of connectionist net- work for general path problems --- p.54Chapter 7.4 --- Experimental Results --- p.55Chapter 7.4.1 --- Convergence time --- p.56Chapter 7.4.2 --- The accuracy of the system --- p.57Chapter 7.5 --- Conclusion --- p.58Chapter 8 --- Transitive Closure Problems --- p.60Chapter 8.1 --- Introduction --- p.60Chapter 8.2 --- Different ways of implementation of BRIN for transitive closure --- p.61Chapter 8.2.1 --- Digital Implementation --- p.61Chapter 8.2.2 --- Analog Implementation --- p.61Chapter 8.3 --- Transitive Closure Problem --- p.63Chapter 8.3.1 --- A special case of maximum spanning tree problem --- p.64Chapter 8.3.2 --- Analog approach solution for transitive closure problem --- p.65Chapter 8.3.3 --- Current-mode approach solution for transitive closure problem --- p.67Chapter 8.4 --- Comparisons between the different forms of implementation of BRIN for transitive closure --- p.71Chapter 8.4.1 --- Convergence Time --- p.71Chapter 8.4.2 --- Circuit complexity --- p.72Chapter 8.5 --- Discussion --- p.73Chapter 9 --- Critical path problems --- p.74Chapter 9.1 --- Introduction --- p.74Chapter 9.2 --- Problem statement and single-destination BRIN solution --- p.75Chapter 9.3 --- Analog implementation --- p.76Chapter 9.3.1 --- Separated building block --- p.78Chapter 9.3.2 --- Combined building block --- p.79Chapter 9.4 --- Current-mode approach --- p.80Chapter 9.4.1 --- "Site function, unit output function and a completed network" --- p.80Chapter 9.5 --- Conclusion --- p.83Chapter 10 --- Conclusions --- p.85Chapter 10.1 --- Summary of Achievements --- p.85Chapter 10.2 --- Future development --- p.88Chapter 10.2.1 --- Application for financial problems --- p.88Chapter 10.2.2 --- Fabrication of VLSI Implementation --- p.88Chapter 10.2.3 --- Actual prototyping of Analog Integrated Circuits for critical path and transitive closure problems --- p.89Chapter 10.2.4 --- Other implementation platform --- p.89Chapter 10.2.5 --- On-line update of routing table inside the router for network com- munication using BRIN --- p.89Chapter 10.2.6 --- Other BRIN's applications --- p.90Bibliography --- p.9

Applications and implementation of neuro-connectionist architectures.

by H.S. Ng.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references (leaves 91-97).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Introduction --- p.1Chapter 1.2 --- Neuro-connectionist Network --- p.2Chapter 2 --- Related Works --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.1.1 --- Kruskal's Algorithm --- p.5Chapter 2.1.2 --- Prim's algorithm --- p.6Chapter 2.1.3 --- Sollin's algorithm --- p.7Chapter 2.1.4 --- Bellman-Ford algorithm --- p.8Chapter 2.1.5 --- Floyd-Warshall algorithm --- p.9Chapter 3 --- Binary Relation Inference Network and Path Problems --- p.11Chapter 3.1 --- Introduction --- p.11Chapter 3.2 --- Topology --- p.12Chapter 3.3 --- Network structure --- p.13Chapter 3.3.1 --- Single-destination BRIN architecture --- p.14Chapter 3.3.2 --- Comparison between all-pair BRIN and single-destination BRIN --- p.18Chapter 3.4 --- Path Problems and BRIN Solution --- p.18Chapter 3.4.1 --- Minimax path problems --- p.18Chapter 3.4.2 --- BRIN solution --- p.19Chapter 4 --- Analog and Voltage-mode Approach --- p.22Chapter 4.1 --- Introduction --- p.22Chapter 4.2 --- Analog implementation --- p.24Chapter 4.3 --- Voltage-mode approach --- p.26Chapter 4.3.1 --- The site function --- p.26Chapter 4.3.2 --- The unit function --- p.28Chapter 4.3.3 --- The computational unit --- p.28Chapter 4.4 --- Conclusion --- p.29Chapter 5 --- Current-mode Approach --- p.32Chapter 5.1 --- Introduction --- p.32Chapter 5.2 --- Current-mode approach for analog VLSI Implementation --- p.33Chapter 5.2.1 --- Site and Unit output function --- p.33Chapter 5.2.2 --- Computational unit --- p.34Chapter 5.2.3 --- A complete network --- p.35Chapter 5.3 --- Conclusion --- p.37Chapter 6 --- Neural Network Compensation for Optimization Circuit --- p.40Chapter 6.1 --- Introduction --- p.40Chapter 6.2 --- A Neuro-connectionist Architecture for error correction --- p.41Chapter 6.2.1 --- Linear Relationship --- p.42Chapter 6.2.2 --- Output Deviation of Computational Unit --- p.44Chapter 6.3 --- Experimental Results --- p.46Chapter 6.3.1 --- Training Phase --- p.46Chapter 6.3.2 --- Generalization Phase --- p.48Chapter 6.4 --- Conclusion --- p.50Chapter 7 --- Precision-limited Analog Neural Network Compensation --- p.51Chapter 7.1 --- Introduction --- p.51Chapter 7.2 --- Analog Neural Network hardware --- p.53Chapter 7.3 --- Integration of analog neural network compensation of connectionist net- work for general path problems --- p.54Chapter 7.4 --- Experimental Results --- p.55Chapter 7.4.1 --- Convergence time --- p.56Chapter 7.4.2 --- The accuracy of the system --- p.57Chapter 7.5 --- Conclusion --- p.58Chapter 8 --- Transitive Closure Problems --- p.60Chapter 8.1 --- Introduction --- p.60Chapter 8.2 --- Different ways of implementation of BRIN for transitive closure --- p.61Chapter 8.2.1 --- Digital Implementation --- p.61Chapter 8.2.2 --- Analog Implementation --- p.61Chapter 8.3 --- Transitive Closure Problem --- p.63Chapter 8.3.1 --- A special case of maximum spanning tree problem --- p.64Chapter 8.3.2 --- Analog approach solution for transitive closure problem --- p.65Chapter 8.3.3 --- Current-mode approach solution for transitive closure problem --- p.67Chapter 8.4 --- Comparisons between the different forms of implementation of BRIN for transitive closure --- p.71Chapter 8.4.1 --- Convergence Time --- p.71Chapter 8.4.2 --- Circuit complexity --- p.72Chapter 8.5 --- Discussion --- p.73Chapter 9 --- Critical path problems --- p.74Chapter 9.1 --- Introduction --- p.74Chapter 9.2 --- Problem statement and single-destination BRIN solution --- p.75Chapter 9.3 --- Analog implementation --- p.76Chapter 9.3.1 --- Separated building block --- p.78Chapter 9.3.2 --- Combined building block --- p.79Chapter 9.4 --- Current-mode approach --- p.80Chapter 9.4.1 --- "Site function, unit output function and a completed network" --- p.80Chapter 9.5 --- Conclusion --- p.83Chapter 10 --- Conclusions --- p.85Chapter 10.1 --- Summary of Achievements --- p.85Chapter 10.2 --- Future development --- p.88Chapter 10.2.1 --- Application for financial problems --- p.88Chapter 10.2.2 --- Fabrication of VLSI Implementation --- p.88Chapter 10.2.3 --- Actual prototyping of Analog Integrated Circuits for critical path and transitive closure problems --- p.89Chapter 10.2.4 --- Other implementation platform --- p.89Chapter 10.2.5 --- On-line update of routing table inside the router for network com- munication using BRIN --- p.89Chapter 10.2.6 --- Other BRIN's applications --- p.90Bibliography --- p.9

Identification de modèles de procédés par programmation mixte déterministe

La recherche de modèles de procédés constitue le thème développé dans ce mémoire. Partant d'une superstructure composée de cellules élémentaires telles que des réacteurs continus, des réacteurs piston, des zones mortes, des by-pass et des recyclages, l'objectif est de déterminer le meilleur arrangement de ces procédés élémentaires pour obtenir une sortie modélisée aussi proche que possible d'une sortie expérimentale. Le problème d'optimisation non linéaire en variables mixtes qui en découle est résolu à l'aide de l'environnement GAMS, plus particulièrement avec les solvers DICOPT++ et SBB. Dans un premier temps l'étude concerne les procédés à fonctionnement en régime permanant, et l'objectif est de déterminer une concentration obtenue par le modèle aussi voisine que possible de la concentration observée expérimentalement. Un bassin de décantation et un réacteur en lit fluidisé pour la déphosphation d'effluents aqueux illustrent la démarche. La seconde partie est relative à l'étude de procédés fonctionnant en régime dynamique. Dans ce cas il s'agit de retrouver une courbe de distribution de temps de séjour analogue à une courbe obtenue expérimentalement. Un local ventilé de l'industrie nucléaire est modélisé suivant cette approche. Dans les deux cas, plusieurs fonctions objectif et plusieurs types de superstructures sont étudiés. ABSTRACT : The search for process models is the goal of this thesis. Starting from a superstructure composed of elementary cells like continuous stirred tank reactors, plug flow reactors, dead-zones, recycles and by-passes, the study aims at determining the best arrangement of these elementary processes in order to obtain a modelled output as close as possible of an experimental response. The resulting mixed-integer nonlinear optimisation problem is solved by means of the GAMS environment, particularly the solvers DICOPT++ and SBB. In a first part, the study is related to steady-state processes, and the goal is to obtain a model giving an output concentration as close as possible of a given experimental concentration. A settling tank and a pellet reactor for phosphorus recovery from wastewater by precipitation of calcium phosphate illustrate the approach. In the second part, where dynamic processes are studied, the objective is to obtain a model giving a residence time distribution curve fitting as well as possible an experimental RDT curve. A ventilated indoor space used in the nuclear field is modelled according to this strategy. n both cases, several objective functions and superstructures are studied