Tolerating multiple faults in multistage interconnection networks with minimal extra stages

Adams and Siegel (1982) proposed an extra stage cube interconnection network that tolerates one switch failure with one extra stage. We extend their results and discover a class of extra stage interconnection networks that tolerate multiple switch failures with a minimal number of extra stages. Adopting the same fault model as Adams and Siegel, the faulty switches can be bypassed by a pair of demultiplexer/multiplexer combinations. It is easy to show that, to maintain point to point and broadcast connectivities, there must be at least S extra stages to tolerate I switch failures. We present the first known construction of an extra stage interconnection network that meets this lower-bound. This 12-dimensional multistage interconnection network has n+f stages and tolerates I switch failures. An n-bit label called mask is used for each stage that indicates the bit differences between the two inputs coming into a common switch. We designed the fault-tolerant construction such that it repeatedly uses the singleton basis of the n-dimensional vector space as the stage mask vectors. This construction is further generalized and we prove that an n-dimensional multistage interconnection network is optimally fault-tolerant if and only if the mask vectors of every n consecutive stages span the n-dimensional vector space

New Free-Space Multistage Optical Interconnection Network and its Matrix Theory

A new free-space multistage optical interconnection network which is called the Comega interconnection network is presented. It has the same topological construction for the cascade stages of the Comega interconnection. The concept of the left Comega and the right Comega interconnection networks are given to describe the whole Comega interconnection network. The matrix theory for the Comega interconnection network is presented. The route controlling of the Comega interconnection network is decided based on the matrix analysis. The node switching states in cascade stages of the 8 by 8 Comega interconnection network for the route selection are given. The data communications between arbitrary input channel with arbitrary output channel can be performed easily

Design of an Efficient Interconnection Network of Temperature Sensors

Temperature has become a first class design constraint because high temperatures adversely affect circuit reliability, static power and degrade the performance. In this scenario, thermal characterization of ICs and on-chip temperature monitoring represent fundamental tasks in electronic design. In this work, we analyze the features that an interconnection network of temperature sensors must fulfill. Departing from the network topology, we continue with the proposal of a very light-weight network architecture based on digitalization resource sharing. Our proposal supposes a 16% improvement in area and power consumption compared to traditional approache

Reduction of connections for multibus organization

The multibus interconnection network is an attractive solution for connecting processors and memory modules in a multiprocessor with shared memory. It provides a throughput which is intermediate between the single bus and the crossbar, with a corresponding intermediate cost.Postprint (published version

Stuttgart Interconnection Network Project from PIX to NICS

The PIX follow-up project NICS is described. The purpose of PIX was access to X.25, the DATEX-P network of the Federal German Post Office. The development and implementation of higher protocols for levels 4-7 in the ISOSINN was the actual problem here. Results of the PIX project are given. NICS (Stuttgart Interconnection Network Project) is presented. International Protocols are reviewed. PAD service is described, which allows terminal access to DATEX-P network of the Federal German Post Office