Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs

Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up self-assembled molecular electronics that are generally assumed to have a high degree of irregularity and imperfection. Here, we pragmatically and experimentally investigate important design trade-offs and properties of an irregular, abstract, yet physically plausible 3D small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, the number of switch nodes, the distribution of long- versus short-range connections, and measure the network's relevant communication characteristics. We further explore the robustness against link failures and the ability and efficiency to solve a simple toy problem, the synchronization task. The results confirm that (1) computation in irregular assemblies is a promising and disruptive computing paradigm for self-assembled nano-scale electronics and (2) that 3D small-world interconnect fabrics with a power-law decaying distribution of shortcut lengths are physically plausible and have major advantages over local 2D and 3D regular topologies

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

Guaranteed passive parameterized model order reduction of the partial element equivalent circuit (PEEC) method

The decrease of IC feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the system under study as a function of design parameters, such as geometrical and substrate features, in addition to frequency (or time). Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters. We propose an innovative PMOR technique applicable to PEEC analysis, which combines traditional passivity-preserving model order reduction methods and positive interpolation schemes. It is able to provide parametric reduced-order models, stable, and passive by construction over a user-defined range of design parameter values. Numerical examples validate the proposed approach

Small Footprint Multilayered Millimeter-Wave Antennas and Feeding Networks for Multi-Dimensional Scanning and High-Density Integrated Systems

This paper overviews the state-of-the-art of substrate integrated waveguide (SIW) techniques in the design and realization of innovative low-cost, low-profile and low-loss (L3) millimeter-wave antenna elements, feeding networks and arrays for various wireless applications. Novel classes of multilayered antenna structures and systems are proposed and studied to exploit the vertical dimension of planar structures to overcome certain limita-tions in standard two-dimensional (2-D) topologies. The developed structures are based on two techniques, namely multi-layer stacked structures and E-plane corners. Differ-ent E-plane structures realised with SIW waveguide are presented, thereby demonstrating the potential of the proposed techniques as in multi-polarization antenna feeding. An array of 128 elements shows low SLL and height gain with just 200g of the total weight. Two versions of 2-D scanning multi-beam are presented, which effectively combine frequency scanning with beam forming networks. Adding the benefits of wide band performance to the multilayer structure, two bi-layer structures are investigated. Different stacked antennas and arrays are demonstrated to optimise the targeted antenna performances in the smallest footprint possible. These structures meet the requirement for developing inexpensive compact millimeter-wave antennas and antenna systems. Different structures and architectures are theoretically and experimentally studied and discussed for specific space- and ground-based appli-cations. Practical issues such as high-density integration and high-volume manufacturability are also addressed