Inadmissible Class of Boolean Functions under Stuck-at Faults

Many underlying structural and functional factors that determine the fault behavior of a combinational network, are not yet fully understood. In this paper, we show that there exists a large class of Boolean functions, called root functions, which can never appear as faulty response in irredundant two-level circuits even when any arbitrary multiple stuck-at faults are injected. Conversely, we show that any other Boolean function can appear as a faulty response from an irredundant realization of some root function under certain stuck-at faults. We characterize this new class of functions and show that for n variables, their number is exactly equal to the number of independent dominating sets (Harary and Livingston, Appl. Math. Lett., 1993) in a Boolean n-cube. We report some bounds and enumerate the total number of root functions up to 6 variables. Finally, we point out several open problems and possible applications of root functions in logic design and testing

In-flight maintenance study Final report

Sample system analysis, MF requirements, redesign, and packaging desig

Randomized encoding of combinational and sequential logic for resistance to hardware Trojans

Globalization of micro-chip fabrication has opened a new avenue of cyber-crime. It is now possible to insert hardware Trojans directly into a chip during the manufacturing process. These hardware Trojans are capable of destroying a chip, reducing performance or even capturing sensitive data. To date, defensive methods have focused on detection of the Trojan circuitry or prevention through design for security methods. This dissertation presents a shift away from prevention and detection to a design methodology wherein one no longer cares if a Trojan is present or not. The Randomized Encoding of Combinational Logic for Resistance to Data Leakage or RECORD process is presented in the first of three papers. This chip design process utilizes dual rail encoding and Quilt Packaging to create a secure combinational design that can resist data leakage even when the full design is known to an attacker. This is done with only a 2.28x-2.33 x area increase and 1.7x-2.24x increase in power. The second paper describes a new method, Sequential RECORD, which introduces additional randomness and moves to 3D split manufacturing to isolate the secure areas of the design. Sequential RECORD is shown to work with 3.75x area overhead and 4.5x power increase with a 3% reduction in slack. Finally, the RECORD concept is refined into a Time Division Multiplexed (TDM) version in the third paper, which reduces area and power overhead by 63% and 56% respectively. A method to safely utilize commercial chips based on the TDM RECORD concept is also demonstrated. This method allows the commercial chip to be operated safely without modification at the cost of latency, which increases by 3.9x --Abstract, page iv

OptCircuit: An optimization based method for computational design of genetic circuits

<p>Abstract</p> <p>Background</p> <p>Recent years has witnessed an increasing number of studies on constructing simple synthetic genetic circuits that exhibit desired properties such as oscillatory behavior, inducer specific activation/repression, etc. It has been widely acknowledged that that task of building circuits to meet multiple inducer-specific requirements is a challenging one. This is because of the incomplete description of component interactions compounded by the fact that the number of ways in which one can chose and interconnect components, increases exponentially with the number of components.</p> <p>Results</p> <p>In this paper we introduce OptCircuit, an optimization based framework that automatically identifies the circuit components from a list and connectivity that brings about the desired functionality. Multiple literature sources are used to compile a comprehensive compilation of kinetic descriptions of promoter-protein pairs. The dynamics that govern the interactions between the elements of the genetic circuit are currently modeled using deterministic ordinary differential equations but the framework is general enough to accommodate stochastic simulations. The desired circuit response is abstracted as the maximization/minimization of an appropriately constructed objective function. Computational results for a toggle switch example demonstrate the ability of the framework to generate the complete list of circuit designs of varying complexity that exhibit the desired response. Designs identified for a genetic decoder highlight the ability of OptCircuit to suggest circuit configurations that go beyond the ones compatible with digital logic-based design principles. Finally, the results obtained from the concentration band detector example demonstrate the ability of OptCircuit to design circuits whose responses are contingent on the level of external inducer as well as pinpoint parameters for modification to rectify an existing (non-functional) biological circuit and restore functionality.</p> <p>Conclusion</p> <p>Our results demonstrate that OptCircuit framework can serve as a design platform to aid in the construction and finetuning of integrated biological circuits.</p

Multipac, a multiple pool processor and computer for a spacecraft central data system

Spacecraft central data system computer used on deep space probe

On the Improving of Approximate Computing Quality Assurance

Approximate computing (AC) has been predominantly recommended for implementation in error-tolerant applications as it offers a reduced resource usage, e.g.,~area and power, for a trade-off in output quality. However, AC implementation has not been adopted in commercial designs yet as it is still falling short in providing a good enough quality. Thus, continued research in the field in the field of improving quality of AC designs is indispensable. In this direction, a recent study exploited the use of machine learning (ML) to improve output quality. Nonetheless, the idea of quality assurance in AC designs could be improved in many aspects. In the work we present in this thesis, we propose a few practical methods to improve an ML-based quality assurance methodology, which consist of an ML-model that select the most suitable design from a library of AC circuits. For instance, we extend the library of AC designs used for the ML-based approach with larger data path circuits. Larger designs, however, result in an exponential growth of complexity. Thus we propose the use of data pre-processing in order to reduce this hurdle by prioritizing designs based on their physical properties. Another direction of improving AC circuits designs in general, and the ML-based model in particular is design space exploration (DSE). We therefore propose a novel DSE that drastically reduces the design space based on the aimed targets for area, latency and power of the AC circuit. Moreover, even with a narrowed design space, the number of AC designs to be assessed for their quality could be enormous. Thus, as part of this thesis, we propose a DSE that uses an intricate mathematical modeling for designs to assess their quality. In another effort in improving quality assurance for AC design, we introduce a highly reliable model that uses a minimal overhead. This work is achieved by using redundant AC modules to form an approximate quadruple modular redundancy (AQMR) design. The proposed AQMR is superior to the exact triple modular redundancy (TMR) by offering a better reliability on top of the resource savings resulting from the implementation of AC

Aggressive aggregation

Among the first steps in a compilation pipeline is the construction of an Intermediate Representation (IR), an in-memory representation of the input program. Any attempt to program optimisation, both in terms of size and running time, has to operate on this structure. There may be one or multiple such IRs, however, most compilers use some form of a Control Flow Graph (CFG) internally. This representation clearly aims at general-purpose programming languages, for which it is well suited and allows for many classical program optimisations. On the other hand, a growing structural difference between the input program and the chosen IR can lose or obfuscate information that can be crucial for effective optimisation. With today’s rise of a multitude of different programming languages, Domain-Specific Languages (DSLs), and computing platforms, the classical machine-oriented IR is reaching its limits and a broader variety of IRs is needed. This realisation yielded, e.g., Multi-Level Intermediate Representation (MLIR), a compiler framework that facilitates the creation of a wide range of IRs and encourages their reuse among different programming languages and the corresponding compilers. In this modern spirit, this dissertation explores the potential of Algebraic Decision Diagrams (ADDs) as an IR for (domain-specific) program optimisation. The data structure remains the state of the art for Boolean function representation for more than thirty years and is well-known for its optimality in size and depth, i.e. running time. As such, it is ideally suited to represent the corresponding classes of programs in the role of an IR. We will discuss its application in a variety of different program domains, ranging from DSLs to machine-learned programs and even to general-purpose programming languages. Two representatives for DSLs, a graphical and a textual one, prove the adequacy of ADDs for the program optimisation of modelled decision services. The resulting DSLs facilitate experimentation with ADDs and provide valuable insight into their potential and limitations: input programs can be aggregated in a radical fashion, at the risk of the occasional exponential growth. With the aggregation of large Random Forests into a single aggregated ADD, we bring this potential to a program domain of practical relevance. The results are impressive: both running time and size of the Random Forest program are reduced by multiple orders of magnitude. It turns out that this ADD-based aggregation can be generalised, even to generaliii purpose programming languages. The resulting method achieves impressive speedups for a seemingly optimal program: the iterative Fibonacci implementation. Altogether, ADDs facilitate effective program optimisation where the input programs allow for a natural transformation to the data structure. In these cases, they have proven to be an extremely powerful tool for the optimisation of a program’s running time and, in some cases, of its size. The exploration of their potential as an IR has only started and deserves attention in future research

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed

The programmable logic controller : its prehistory, emergence and application

Programmable Logic Controllers (PLCs) are widely used devices controlling industrial machines and processes and many other diverse applications, requiring primarily, combinatorial logic and sequential control. The PLC is a hidden technology, little known by the general public and overlooked in academic historical studies of technology. The research reported in this thesis aims to address this lack of awareness. The thesis explores the development of sequential and combinatorial logic control technologies, the emergence of the PLC, its subsequent development and its industrial applications. Patents and first- hand accounts and experiences from senior industrial engineers in a number of diverse manufacturing industries have been used as the primary research sources since, as a hidden technology, academic historical accounts are sparse. This approach illustrates, through using the PLC as an example, a potential method of studying other, unrelated hidden technologies. The research has revealed the influence of geography, industrial settings and earlier engineering practices on the design, selection and application of PLC control technologies, and comments on the how these influences define specific communities of practice