An On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18- m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average

Development and test results of a readout chip for the GERDA experiment

This paper describes the F-CSA104 architecture and its measurement results. The F-CSA104 is for γ spectroscopy with Ge detectors. It is a low noise, fully integrated, four channel XFAB 0.6μm CMOS technology ASIC, that has been developed for the GERDA experiment. Each channel contains a charge sensitive preamplifier (CSA) followed by a 11.7MHz differential line driver. It has been particularly designed to operate in liquid argon (T = 87K/-186°C) and to have a measuring sensitivity of 660e- with an ENC of 110e-, after offline filtering with 10μs shaping, when connected to a 30pF load. Special techniques are used to improve the SNR such as a large input PMOS FET, an integrated 500MΩ CSA feedback resistor and a noise degeneration drain resistor

Accuracy of Microwave Transistor fT and fMAX Extractions

We present a complete methodology to evaluate the accuracy of microwave transistor figures-of-merit fT (current gain cut-off frequency) and fMAX (maximum oscillation frequency). These figures-of-merit are usually extracted from calibrated S-parameter measurements affected by residual calibration and measurement uncertainties. Thus, the uncertainties associated to fT and fMAX can be evaluated only after an accurate computation of the S-parameters uncertainties, including the contribution from de-embedding. This was done with the aid of two recently released software tools. We also present an analysis on how different interpolation/extrapolation methodologies affect uncertainty. Finally, an overview of the possible causes of errors and suggestions on how to avoid them are given. With the continued rise of reported fT /fMAX values, this study has become necessary in order to add confidence intervals to these figures-of-meri

Resource efficient on-node spike sorting

Current implantable brain-machine interfaces are recording multi-neuron activity by utilising multi-channel, multi-electrode micro-electrodes. With the rapid increase in recording capability has come more stringent constraints on implantable system power consumption and size. This is even more so with the increasing demand for wireless systems to increase the number of channels being monitored whilst overcoming the communication bottleneck (in transmitting raw data) via transcutaneous bio-telemetries. For systems observing unit activity, real-time spike sorting within an implantable device offers a unique solution to this problem. However, achieving such data compression prior to transmission via an on-node spike sorting system has several challenges. The inherent complexity of the spike sorting problem arising from various factors (such as signal variability, local field potentials, background and multi-unit activity) have required computationally intensive algorithms (e.g. PCA, wavelet transform, superparamagnetic clustering). Hence spike sorting systems have traditionally been implemented off-line, usually run on work-stations. Owing to their complexity and not-so-well scalability, these algorithms cannot be simply transformed into a resource efficient hardware. On the contrary, although there have been several attempts in implantable hardware, an implementation to match comparable accuracy to off-line within the required power and area requirements for future BMIs have yet to be proposed. Within this context, this research aims to fill in the gaps in the design towards a resource efficient implantable real-time spike sorter which achieves performance comparable to off-line methods. The research covered in this thesis target: 1) Identifying and quantifying the trade-offs on subsequent signal processing performance and hardware resource utilisation of the parameters associated with analogue-front-end. Following the development of a behavioural model of the analogue-front-end and an optimisation tool, the sensitivity of the spike sorting accuracy to different front-end parameters are quantified. 2) Identifying and quantifying the trade-offs associated with a two-stage hybrid solution to realising real-time on-node spike sorting. Initial part of the work focuses from the perspective of template matching only, while the second part of the work considers these parameters from the point of whole system including detection, sorting, and off-line training (template building). A set of minimum requirements are established which ensure robust, accurate and resource efficient operation. 3) Developing new feature extraction and spike sorting algorithms towards highly scalable systems. Based on waveform dynamics of the observed action potentials, a derivative based feature extraction and a spike sorting algorithm are proposed. These are compared with most commonly used methods of spike sorting under varying noise levels using realistic datasets to confirm their merits. The latter is implemented and demonstrated in real-time through an MCU based platform.Open Acces

Accurate Characterization of Silicon-On-Insulator MOSFETs for the Design of Low-Voltage, Low-Power RF Integrated Circuits

The maturation of low cost Silicon-on-Insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in-situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static small-signal model and the high-frequency noise parameters for MOSFETs. The extracted model is shown to be valid up to 40 GHz.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/44055/1/10470_2004_Article_271487.pd

Etude et caractérisation d'un capteur en silicium amorphe hydrogéné déposé sur circuit intégré pour la détection de particules et de rayonnements

Next generation experiments at the European laboratory of particle physics (CERN) require particle detector alternatives to actual silicon detectors. This thesis presents a novel detector technology, which is based on the deposition of a hydrogenated amorphous silicon sensor on top of an integrated circuit. Performance and limitations of this technology have been assessed for the first time in this thesis in the context of particle detectors. Specific integrated circuits have been designed and the detector segmentation, the interface sensor â chip and the sensor leakage current have been studied in details. The signal induced by the track of an ionizing particle in the sensor has been characterized and results on the signal speed, amplitude and on the sensor resistance to radiation are presented. The results are promising regarding the use of this novel technology for radiation detection, though limitations have been shown for particle physics application

Optical characteristics of pn junctions and MOS transistors with applications to integrated circuit measurements

The photocurrent generation characteristics of pn junctions and MOS transistors are studied with a view to applying these devices to input data optically direct into the internal circuity of integrated circuits, by a finely focussed laser beam. This permits simple testing schemes for fault detection; and can make large savings in the time taken for diagnostic testing of IC's. A review of the spectral characteristics of the photocurrents of both the diffused pn junction and the MOS (induced) pn junction are presented and compared. It is also shown that the optical input of data can be employed to measure propagation delay times associated with each stage in an MOS dynamic shift-register circuit; which leads to a better understanding of the internal operation of the circuit. A novel application of the MOS phototransistor is also presented. It is shown that amplification of the photocurrent generated can be produced by including a large resistance between the substrate and the source. A simple model which adequately describes the mechanisms involved is presented. Results of calculations of both the amplification factor and the response speed, based on this model show good agreement with experiment.This configuration can be used to produce from a moderate laser beam power, the large photocurrents needed to switch some digital IC families (e.g. CMOS). Silicon-gate devices are very suitable as MOS phototransistors because the gate electrode transmits visible radiation. This property, coupled with photocurrent amplification where necessary, makes the laser probe method of data input in conjunction with standard test equipment a useful method for testing of present day MOS integrated circuits.</p