Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits

Abstract. This work in progress report proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. This is in contrast to existing literature where nearest neighbor constraints are usually considered at the quantum circuit level. In order to define the metric, investigations on a state-of-the-art reversible to quantum mapping scheme have been conducted. From the retrieved information, a proper estimation to be used as a cost metric has been obtained. Using the metric, it becomes possible for the first time to optimize a reversible circuit with respect to nearest neighbor constraints

Scalable Design and Synthesis of Reversible Circuits

The expectations on circuits are rising with their number of applications, and technologies alternative to CMOS are becoming more important day by day. A promising alternative is reversible computation, a computing paradigm with applications in quantum computation, adiabatic circuits, program inversion, etc. An elaborated design flow is not available to reversible circuit design yet. In this work, two directions are considered: Exploiting the conventional design flow and developing a new flow according to the properties of reversible circuits. Which direction should be taken is not obvious, so we discuss the possible assets and drawbacks of taking either direction. We present ideas which can be exploited and outline open challenges which still have to be addressed. Preliminary results obtained by initial implementations illustrate the way to go. By this we present and discuss two promising and complementary directions for the scalable design and synthesis of reversible circuits

Synthesis and evaluation of fault-tolerant quantum computer architectures

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 241-247).Fault-tolerance is the cornerstone of practical, large-scale quantum computing, pushed into its prominent position with heroic theoretical efforts. The fault-tolerance threshold, which is the component failure probability below which arbitrarily reliable quantum computation becomes possible, is one standard quality measure of fault-tolerant designs based on recursive simulation. However, there is a gulf between theoretical achievements and the physical reality and complexity of envisioned quantum computing systems. This thesis takes a step toward bridging that gap. We develop a new experimental method for estimating fault-tolerance thresholds that applies to realistic models of quantum computer architectures, and demonstrate this technique numerically. We clarify a central problem for experimental approaches to fault-tolerance evaluation--namely, distinguishing between potentially optimistic pseudo-thresholds and actual thresholds that determine scalability. Next, we create a system architecture model for the trapped-ion quantum computer, discuss potential layouts, and numerically estimate the fault-tolerance threshold for this system when it is constrained to a local layout. Finally, we place the problem of evaluation and synthesis of fault-tolerant quantum computers into a broader framework by considering a software architecture for quantum computer design.by Andrew W. Cross.S.M