105,815 research outputs found

    Low Power Resonant Rotary Global Clock Distribution Network Design

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    Along with the increasing complexity of the modern very large scale integrated (VLSI) circuit design, the power consumption of the clock distribution network in digital integrated circuits is continuously increasing. In terms of power and clock skew, the resonant clock distribution network has been studied as a promising alternative to the conventional clock distribution network. Resonant clock distribution network, which works based on adiabatic switching principles, provides a complete solution for on-chip clock generation and distribution for low-power and low-skew clock network designs for high-performance synchronous VLSI circuits.This dissertation work aims to develop the global clock distribution network for one kind of resonant clocking technologies: The resonant rotary clocking technology. The following critical aspects are addressed in this work: (1) A novel rotary oscillator array (ROA) topology is proposed to solve the signal rotation direction uniformity problem, in order to support the design of resonant rotary clocking based low-skew clock distribution network; (2) A synchronization scheme is proposed to solve the large scale rotary clocking generation circuit synchronization problem; (3) A low-skew rotary clock distribution network design methodology is proposed with frequency, power and skew optimizations; (4) A resonant rotary clocking based physical design flow is proposed, which can be integrated in the current mainstream IC design flow; (5) A dynamic rotary frequency divider is proposed for dynamic frequency scaling applications. Experimental and theoretical results show: (1) The efficiency of the proposed methodology in the construction of low-skew, low-power resonant rotary clock distribution network. (2) The effectiveness of the dynamic rotary frequency divider in extending the operating frequency range of the low-power resonant rotary based applications.Ph.D., Electrical Engineering -- Drexel University, 201

    Effect of Clock and Power Gating on Power Distribution Network Noise in 2D and 3D Integrated Circuits

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    In this work, power supply noise contribution, at a particular node on the power grid, from clock/power gated blocks is maximized at particular time and the synthetic gating patterns of the blocks that result in the maximum noise is obtained for the interval 0 to target time. We utilize wavelet based analysis as wavelets are a natural way of characterizing the time-frequency behavior of the power grid. The gating patterns for the blocks and the maximum supply noise at the Point of Interest at the specified target time obtained via a Linear Programming (LP) formulation (clock gating) and Genetic Algorithm based problem formulation (Power Gating)

    High performance IC clock networks with grid and tree topologies

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    In this dissertation, an essential step in the integrated circuit (IC) physical design flow—the clock network design—is investigated. Clock network design entailsa series of computationally intensive, large-scale design and optimization tasks for the generation and distribution of the clock signal through different topologies. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research. The synthesis and optimization methods for the two most commonly used clock topologies in IC design—the grid topology and the tree topology—are primarily investigated.The clock mesh network, which uses the grid topology, has very low skew variation at the cost of high power dissipation. Two novel clock mesh network designmethodologies are proposed in this dissertation in order to reduce the power dissipation. These are the first methods known in literature that combine clock meshsynthesis with incremental register placement and clock gating for power saving purposes. The application of the proposed automation methods on the emerging resonant rotary clocking technology, which also has the grid topology, is investigated in this dissertation as well.The clock tree topology has the advantage of lower power dissipation compared to other traditional clock topologies (e.g. clock mesh, clock spine, clock tree with cross links) at the cost of increased performance degradation due to on-chip variations. A novel clock tree buffer polarity assignment flow is proposed in this dissertation in order to reduce these effects of on-chip variations on the clock tree topology. The proposed polarity assignment flow is the first work that introduces post-silicon, dynamic reconfigurability for polarity assignment, enabling clock gating for low power operation of the variation-tolerant clock tree networks.Ph.D., Electrical Engineering -- Drexel University, 201

    Modeling of thermally induced skew variations in clock distribution network

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    Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

    Variant X-Tree Clock Distribution Network and Its Performance Evaluations

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    All-optical membrane InP switch on silicon for access applications

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    Using an integrated membrane switch on SOI, optical clock distribution is achieved while all-optical switching of datapackets is maintained. Transmission through 25km SMF is demonstrated with 1.5dB penalty, limited by signal OSNR and pump extinction

    Radiation safety based on the sky shine effect in reactor

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    In the reactor operation, neutrons and gamma rays are the most dominant radiation. As protection, lead and concrete shields are built around the reactor. However, the radiation can penetrate the water shielding inside the reactor pool. This incident leads to the occurrence of sky shine where a physical phenomenon of nuclear radiation sources was transmitted panoramic that extends to the environment. The effect of this phenomenon is caused by the fallout radiation into the surrounding area which causes the radiation dose to increase. High doses of exposure cause a person to have stochastic effects or deterministic effects. Therefore, this study was conducted to measure the radiation dose from sky shine effect that scattered around the reactor at different distances and different height above the reactor platform. In this paper, the analysis of the radiation dose of sky shine effect was measured using the experimental metho

    Optically reconfigurable 1 x 4 remote node switch for access networks

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    In this paper we demonstrate an optically controlled 1 x 4 remote node switch, based on membrane InP switches bonded to a silicon-on-insulator circuit. We show that the switch exhibits cross talk better than 25 dB between the output ports, and that the switch operates without receiver sensitivity penalty. Furthermore, the proposed switch architecture allows for optical clock distribution as a means to avoid the need for clock recovery at the receiver side. This is demonstrated in a proof-of-principle experiment where data and clock are sent through a single membrane InP switch

    Coherent optical phase transfer over a 32-km fiber with 1-s instability at 101710^{-17}

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    The phase coherence of an ultrastable optical frequency reference is fully maintained over actively stabilized fiber networks of lengths exceeding 30 km. For a 7-km link installed in an urban environment, the transfer instability is 6×10186 \times 10^{-18} at 1-s. The excess phase noise of 0.15 rad, integrated from 8 mHz to 25 MHz, yields a total timing jitter of 0.085 fs. A 32-km link achieves similar performance. Using frequency combs at each end of the coherent-transfer fiber link, a heterodyne beat between two independent ultrastable lasers, separated by 3.5 km and 163 THz, achieves a 1-Hz linewidth.Comment: 4 pages, 4 figure
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