Energy efficient microprocessor platform based on instructional level parallelism

Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a schedule allocates the data and schedule to a plurality of computational units. The scheduler also modifies voltage and frequency settings of the processing architecture to optimize power consumption and throughput of the system. The computational units include control units and execute units. The control units receive and decode the instructions and send the decoded instructions to execute units. The execute units then execute the instructions according to relevant software.</p

Investigating the impact of image content on the energy efficiency of hardware-accelerated digital spatial filters

Battery-operated low-power portable computing devices are becoming an inseparable part of human daily life. One of the major goals is to achieve the longest battery life in such a device. Additionally, the need for performance in processing multimedia content is ever increasing. Processing image and video content consume more power than other applications. A widely used approach to improving energy efficiency is to implement the computationally intensive functions as digital hardware accelerators. Spatial filtering is one of the most commonly used methods of digital image processing. As per the Fourier theory, an image can be considered as a two-dimensional signal that is composed of spatially extended two-dimensional sinusoidal patterns called gratings. Spatial frequency theory states that sinusoidal gratings can be characterised by its spatial frequency, phase, amplitude, and orientation. This article presents results from our investigation into assessing the impact of these characteristics of a digital image on the energy efficiency of hardware-accelerated spatial filters employed to process the same image. Two greyscale images each of size 128 × 128 pixels comprising two-dimensional sinusoidal gratings at maximum spatial frequency of 64 cycles per image orientated at 0° and 90°, respectively, were processed in a hardware implemented Gaussian smoothing filter. The energy efficiency of the filter was compared with the baseline energy efficiency of processing a featureless plain black image. The results show that energy efficiency of the filter drops to 12.5% when the gratings are orientated at 0° whilst rises to 72.38% at 90°

Thermal stratification in a liquid storage tank using an inlet porous manifold.

In the second part, a storage tank was constructed. The dimensions were kept as close as possible to those used in the previous study. A number of experiments were conducted to investigate the conditions necessary for stratification. Flow visualization experiments were also conducted to evaluate the effectiveness of the inlet porous manifold in promoting and maintaining the thermal stratification.This work investigated the conditions necessary for thermal stratification in liquid storage tank. The investigation involved the fabrication and testing of a porous manifold to determine its permeability and the slip coefficient that can be used at the interface between the porous wall and the fluid layer. A full-scale model of a thermal storage tank with an aspect ratio of 4 (l/r t = 4) using an inlet porous manifold was constructed and tested. The results were compared to those obtained from a numerical model of the same tank. After validation, the numerical model was used to further investigate the conditions necessary for thermal stratification. In general, this work was carried out in three major parts.Finally, a numerical simulation of the thermal storage tank was conducted. A comparison with the experimental results was performed to evaluate the accuracy of the permeability and the slip coefficient measured in the first part of the study. It was then used to evaluate stratification at lower Richardson numbers.In the first part, fiberglass and nylon nettings were used to fabricate seven porous tubes, with various dimensions. Six tubes had an outer diameter of 1.9 cm and wall thickness ranging from 0.158 cm to 0.635 cm, and the other tube had dimensions of 10 cm outer diameter and wall thickness of 0.635 cm. The larger tube was similar to the inlet manifold used in the storage tank. Theoretical analysis for flow in a porous tube was first conducted. The solution was obtained using the slip coefficient condition at the interface between the porous wall and the fluid layer. Experiments were conducted to determine the permeability of each tube in both longitudinal and radial directions, and the slip coefficient that can be used at the interface. Due to the limitations in the present setup, the longitudinal permeability of the large tube was not measured but was estimated from a smaller tube of the same material and a similar wall thickness.Based on the results obtained, it was concluded that slip coefficient depended not only on the material but also on the Reynolds number, the permeability and the porous wall thickness. The longitudinal permeability depended on the material while the radial permeability was found to depend on the wall thickness. (Abstract shortened by UMI.

The design and implementation of a C compiler for SAFA

Master'sMASTER OF SCIENC

Instructional Level Parallelism

Abstract—This paper is a review of the developments in Instruction level parallelism. It takes into account all the changes made in speeding up the execution. The various drawbacks and dependencies due to pipelining are discussed and various solutions to overcome them are also incorporated. It goes ahead in the last section to explain where is the new research leading us

Energy efficient microprocessor platform based on instructional level parallelism

\u3cp\u3eEmbodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a schedule allocates the data and schedule to a plurality of computational units. The scheduler also modifies voltage and frequency settings of the processing architecture to optimize power consumption and throughput of the system. The computational units include control units and execute units. The control units receive and decode the instructions and send the decoded instructions to execute units. The execute units then execute the instructions according to relevant software.\u3c/p\u3