OFDM based air interfaces for future mobile satellite systems

This thesis considers the performance of OFDM in a non-linear satellite channel and mechanisms for overcoming the degradations resulting from the high PAPR in the OFDM signal in the specific satellite architecture. It was motivated by new S-DMB applications but its results are applicable to any OFDM system via satellites. Despite many advantages of OFDM, higher PAPR is a major drawback. OFDM signals are therefore very sensitive to non-linear distortion introduced by the power amplifiers and thus, significantly reduce the power efficiency of the system, which is already crucial to satellite system economics. Simple power amplifier back-off to cope with high OFDM PAPR is not possible. Two transmitter based techniques have been considered: PAPR reduction and amplifier linearization.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Why Is White Noise Not Enough? Using Radio Front-End Models While Designing 6G PHY, Journal of Telecommunications and Information Technology, 2023, nr 2

Each subsequent generation of wireless standards imposes stricter spectral and energy efficiency demands. So far, layered wireless transceiver architectures have been used, allowing for instance to separate channel decoding algorithms from the front-end design. Such an approach may need to be reconsidered in the upcoming 6G era. Especially hardware-originated distortions have to be taken into account while designing other layer algorithms, as high throughput and energy efficiency requirements will push these devices to their limits, revealing their non-linear characteristics. In such a context, this paper will shed some light on the new degrees of freedom enjoyed while cross-layer designing as well as controlling multicarrier and multiantenna transceivers in 6G systems

Design and implementation of an ETSI-SDR OFDM transmitter with power amplifier linearizer

Satellite radio has attained great popularity because of its wide range of geographical coverage and high signal quality as compared to the terrestrial broadcasts. Most Satellite Digital Radio (SDR) based systems favor multi-carrier transmission schemes, especially, orthogonal frequency division multiplexing (OFDM) transmission because of high data transfer rate and spectral efficiency. It is a challenging task to find a suitable platform that supports fast data rates and superior processing capabilities required for the development and deployment of the new SDR standards. Field programmable gate array (FPGA) devices have the potential to become suitable development platform for such standards. Another challenging factor in SDR systems is the distortion of variable envelope signals used in OFDM transmission by the nonlinear RF power amplifiers (PA) used in the base station transmitters. An attractive option is to use a linearizer that would compensate for the nonlinear effects of the PA. In this research, an OFDM transmitter, according to European Telecommunications Standard Institute (ETSI) SDR Technical Specifications 2007-2008, was designed and implemented on a low-cost Xilinx FPGA platform. A weakly nonlinear PA, operating in the L-band SDR frequency (1.450-1.490GHz), was used for signal transmission. An FPGA-based, low-cost, adaptive linearizer was designed and implemented based on the digital predistortion (DPD) reference design from Xilinx, to correct the distortion effects of the PA on the transmitted signal

A 39GHz Balanced Power Amplifier with Enhanced Linearity in 45 nm SOI CMOS

With the high data rate communication systems that come with fifth-generation (5G) mobile networks, the shift of operation to millimeter-wave frequency becomes inevitable. The expected data rate in 5G is significantly improved over 4G by utilizing the large available channel bandwidth at millimeter wave frequencies and complex data modulation schemes. With this increase in operation frequency, many new challenges arise and research efforts are made to tackle them. Among them, the phased array system is one of the hottest topics as it can be made use of to improve the link budget and overcome the path loss challenge at these frequencies. As the last circuit component in the transmitter's front-end right before the antenna, the power amplifier (PA) is one of the most crucial components with significant effects on overall system performance. Many of the traditional challenges of CMOS PA design such as output power and efficiency, are now compounded with the additional challenges that are imposed on complementary metal-oxide semiconductor (CMOS) PAs in millimeter wave phased array systems. This thesis presents a balanced power amplifier design with enhanced linearity in GlobalFoundries' 45nm silicon-on-insulator (SOI) CMOS technology. By using the balanced topology with each stage terminating with a differential 2-stacked architecture, the PA achieves saturated output power of over 21 dBm. Each of the two identical sub-PAs in the balanced topology uses 2-stage topology with driver and PA co-design method. The linearity is enhanced through careful choice of biasing point and a strategic inter-stage matching network design methodology, resulting in amplitude-to-phase distortion below 1 degree up to the output 1dB compression level of over 19 dBm. The balanced amplifier topology significantly reduces the PA performance variation over mismatched load impedance at the output, thus improving the PA performance over different antenna active impedance caused by varying phased array beam-steering angles. In addition to this, the balanced topology also optimizes the PA input and output return loss, giving a better matching than -20 dB at both input and output, and minimizing the risk of potential issues and performance degradation in the system integration phase. Lastly, the compact transformer based matching networks and quadrature hybrids reduce the chip area occupation of this PA, resulting in a compact design with competitive performance