Advances on CMOS image sensors

This paper offers an introduction to the technological advances of image sensors designed using complementary metal–oxide–semiconductor (CMOS) processes along the last decades. We review some of those technological advances and examine potential disruptive growth directions for CMOS image sensors and proposed ways to achieve them. Those advances include breakthroughs on image quality such as resolution, capture speed, light sensitivity and color detection and advances on the computational imaging. The current trend is to push the innovation efforts even further as the market requires higher resolution, higher speed, lower power consumption and, mainly, lower cost sensors. Although CMOS image sensors are currently used in several different applications from consumer to defense to medical diagnosis, product differentiation is becoming both a requirement and a difficult goal for any image sensor manufacturer. The unique properties of CMOS process allows the integration of several signal processing techniques and are driving the impressive advancement of the computational imaging. With this paper, we offer a very comprehensive review of methods, techniques, designs and fabrication of CMOS image sensors that have impacted or might will impact the images sensor applications and markets

Advanced III-V / Si nano-scale transistors and contacts: Modeling and analysis

The exponential miniaturization of Si CMOS technology has been a key to the electronics revolution. However, the continuous downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Hence, novel devices and better channel materials than Si are considered to improve the metal-oxide-semiconductor field-effect transistors (MOSFETs) device performance. III-V compound semiconductors and multi-gate structures are being considered as promising candidates in the next CMOS technology. III-V and Si nano-scale transistors in different architectures are investigated (1) to compare the performance between InGaAs of III-V compound semiconductors and strained-Si in planar FETs and triple-gate non-planar FinFETs. (2) to demonstrate whether or not these technologies are viable alternatives to Si and conventional planar FETs. The simulation results indicate that III-V FETs do not outperform Si FETs in the ballistic transport regime, and triple-gate FinFETs surely represent the best architecture for sub-15nm gate contacts, independently from the choice of channel material. ^ This work also proves that the contact resistance becomes a limiting factor of device performance as it takes larger fraction of the total on-state resistance. Hence, contact resistance must be reduced to meet the next ITRS requirements. However, from a modeling point of view, the understanding of the contacts still remains limited due to its size and multiple associated scattering effects, while the intrinsic device performance can be projected. Therefore, a precise theoretical modeling is required to advance optimized contact design to improve overall device performance. In this work, various factors of the contact resistances are investigated within realistic contact-to-channel structure of III-V quantum well field-effect transistors (QWFET). The key finding is that the contact-to-channel resistance is mainly caused by structural reasons: 1) barriers between multiple layers in the contact region 2) Schottky barrier between metal and contact pad. These two barriers work as bottleneck of the system conductance. The extracted contact resistance matches with the experimental value. The approximation of contact resistance from quantum transport simulation can be very useful to guide better contact designs of the future technology nodes. ^ The theoretical modeling of these nano-scale devices demands a proper treatment of quantum effects such as the energy-level quantization caused by strong quantum confinement of electrons and band structure non-parabolicity. 2-D and 3-D quantum transport simulator that solves non-equilibrium Green\u27s functions (NEGF) transport and Poisson equations self-consistently within a real-space effective mass approximation. The sp3d5s* empirical tight-binding method is employed to include non-parabolicity to obtain more accurate effective masses in confined nano-structures. The accomplishment of this work would aid in designing, engineering and manufacturing nano-scale devices, as well as next-generation microchips and other electronics with nano-scale features

Field Effect Transistor Nanosensor for Breast Cancer Diagnostics

Silicon nanochannel field effect transistor (FET) biosensors are one of the most promising technologies in the development of highly sensitive and label-free analyte detection for cancer diagnostics. With their exceptional electrical properties and small dimensions, silicon nanochannels are ideally suited for extraordinarily high sensitivity. In fact, the high surface-to-volume ratios of these systems make single molecule detection possible. Further, FET biosensors offer the benefits of high speed, low cost, and high yield manufacturing, without sacrificing the sensitivity typical for traditional optical methods in diagnostics. Top down manufacturing methods leverage advantages in Complementary Metal Oxide Semiconductor (CMOS) technologies, making richly multiplexed sensor arrays a reality. Here, we discuss the fabrication and use of silicon nanochannel FET devices as biosensors for breast cancer diagnosis and monitoring

Nanometer-scale InGaAs Field-Effect Transistors for THz and CMOS technologies

Integrated circuits based on InGaAs Field Effect Transistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and space communication systems. InGaAs ICs are also under intense research for new millimeter-wave applications such as collision avoidance radar and gigabit WLANs. InGaAs FET scaling has nearly reached the end of the road and further progress to propel this technology to the THz regime will require significant device innovations. Separately, as Si CMOS faces mounting difficulties to maintain its historical density scaling path, InGaAs-channel MOSFETs have recently emerged as a credible alternative for mainstream logic technology capable of scaling to the 10 nm node and below. To get to this point, fundamental technical problems had to be solved though there are still many challenges to be addressed before the first non-Si CMOS technology becomes a reality. The intense research that this exciting prospect is generating is also reinvigorating the prospects of InGaAs FETs to become the first true THz electronics technology. This paper reviews progress and challenges of InGaAs-based FET technology for THz and CMOS.Focus Center Research Program. Center for Materials, Structures and DevicesIntel CorporationUnited States. Army Research LaboratorySemiconductor Research Corporatio