Total dose evaluation of deep submicron CMOS imaging technology through elementary device and pixel array behavior analysis

Ionizing radiation effects on CMOS image sensors (CIS) manufactured using a 0.18 µm imaging technology are presented through the behavior analysis of elementary structures, such as field oxide FET, gated diodes, photodiodes and MOSFETs. Oxide characterizations appear necessary to understand ionizing dose effects on devices and then on image sensors. The main degradations observed are photodiode dark current increases (caused by a generation current enhancement), minimum size NMOSFET off-state current rises and minimum size PMOSFET radiation induced narrow channel effects. All these effects are attributed to the shallow trench isolation degradation which appears much more sensitive to ionizing radiation than inter layer dielectrics. Unusual post annealing effects are reported in these thick oxides. Finally, the consequences on sensor design are discussed thanks to an irradiated pixel array and a comparison with previous work is discussed

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

We present here a study on both CMOS sensors and elementary structures (photodiodes and in-pixel MOSFETs) manufactured in a deep submicron process dedicated to imaging. We designed a test chip made of one 128×128-3T-pixel array with 10 µm pitch and more than 120 isolated test structures including photodiodes and MOSFETs with various implants and different sizes. All these devices were exposed to ionizing radiation up to 100 krad and their responses were correlated to identify the CMOS sensor weaknesses. Characterizations in darkness and under illumination demonstrated that dark current increase is the major sensor degradation. Shallow trench isolation was identified to be responsible for this degradation as it increases the number of generation centers in photodiode depletion regions. Consequences on hardness assurance and hardening-by-design are discussed

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Analysis of total dose-induced dark current in CMOS image sensors from interface state and trapped charge density measurements

The origin of total ionizing dose induced dark current in CMOS image sensors is investigated by comparing dark current measurements to interface state density and trapped charge density measurements. Two types of photodiode and several thick-oxide-FETs were manufactured using a 0.18-µm CMOS image sensor process and exposed to 10-keV X-ray from 3 krad to 1 Mrad. It is shown that the radiation induced trapped charge extends the space charge region at the oxide interface, leading to an enhancement of interface state SRH generation current. Isochronal annealing tests show that STI interface states anneal out at temperature lower than 100°C whereas about a third of the trapped charge remains after 30 min at 300°C

Experimental study of electron velocity overshoot in silicon inversion layers

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Physics, 1994.Includes bibliographical references (leaves 127-133).by Hang Hu.Ph.D

Silicon-on-insulator MOSFETS: Material, process and device characteristics

NMOS and PMOS Single-crystal-silicon-on-insulator (SOI) MOSFETs have been fabricated at RIT using a Bonded and Etched-back process for substrate formation. A test chip, containing inverters, contact and sheet resistance structures, and various NMOS and PMOS transistors, was fabricated on a 2000A SOI substrate formed by a Bonded and Etched-back technique. Effective mobilities, subthreshold swings, and threshold voltages of the fabricated devices were extracted to investigate the impact of a Bonded and Etched-back process on device performance. A hole mobility of 486 cm2/V-s was obtained in PMOS SOI, comparable to state-of-the-art, and exceeding any mobility previously reported at RIT. A subthreshold swing of 11OmV/decade was observed in PMOS SOI. The NMOS devices were found to be inferior to those fabricated external to RIT using this SOI process. It was found that hole mobility increased by 14% on average and electron mobility increased by 6% on average for SOI devices compared to similar conventional devices fabricated in bulk silicon. Subthreshold swing decreased 93% on average for SOI devices compared to conventional bulk-silicon devices. SOI is identified as an attractive process, having significant performance advantages over bulk-silicon devices

Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs

With a unified physics-based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process-induced and global-induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon-germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature. A dual channel heterostructure consisting of strained Si/Si1-xGex on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics-based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n-channel drive currents of 0.43 and 0.98 mA/Gm, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device