Retiming and Resynthesis with Sweep Are Complete for Sequential Transformation

Abstract-There is a long history of investigations and debates on whether a sequence of retiming and resynthesis is complete for all sequential transformations (on steady states). It has been shown that the sweep operation, which adds or removes registers not used by any output, is necessary for some sequential transformations. However, it is an open question whether retiming and resynthesis with sweep are complete. This paper proves that the operations are complete, but with one caveat: at least one resynthesis operation needs to look through the register boundary into the logic of previous cycle. We showed that this one-cycle reachability is required for retiming and resynthesis to be complete for re-encodings with different code length. This requirement comes from the fact that Boolean circuit is used for a discrete function thus its range needs to be computed by a traversal of the circuit. In theory, five operations in the order of sweep, resynthesis, retiming, resynthesis, and sweep are already complete. However, some practical limitations on resynthesis must be considered. The complexity of retiming and resynthesis verification is also discussed

Energy-Efficient Digital Circuit Design using Threshold Logic Gates

abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths. Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits.Dissertation/ThesisDoctoral Dissertation Computer Science 201

Design, Analysis and Test of Logic Circuits under Uncertainty.

Integrated circuits are increasingly susceptible to uncertainty caused by soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects become detrimental to circuit reliability. In order to address this, we develop methods for analyzing, designing, and testing circuits subject to probabilistic effects. Our main contributions are: 1) a fast, soft-error rate (SER) analyzer that uses functional-simulation signatures to capture error effects, 2) novel design techniques that improve reliability using little area and performance overhead, 3) a matrix-based reliability-analysis framework that captures many types of probabilistic faults, and 4) test-generation/compaction methods aimed at probabilistic faults in logic circuits. SER analysis must account for the main error-masking mechanisms in ICs: logic, timing, and electrical masking. We relate logic masking to node testability of the circuit and utilize functional-simulation signatures, i.e., partial truth tables, to efficiently compute estability (signal probability and observability). To account for timing masking, we compute error-latching windows (ELWs) from timing analysis information. Electrical masking is incorporated into our estimates through derating factors for gate error probabilities. The SER of a circuit is computed by combining the effects of all three masking mechanisms within our SER analyzer called AnSER. Using AnSER, we develop several low-overhead techniques that increase reliability, including: 1) an SER-aware design method that uses redundancy already present within the circuit, 2) a technique that resynthesizes small logic windows to improve area and reliability, and 3) a post-placement gate-relocation technique that increases timing masking by decreasing ELWs. We develop the probabilistic transfer matrix (PTM) modeling framework to analyze effects beyond soft errors. PTMs are compressed into algebraic decision diagrams (ADDs) to improve computational efficiency. Several ADD algorithms are developed to extract reliability and error susceptibility information from PTMs representing circuits. We propose new algorithms for circuit testing under probabilistic faults, which require a reformulation of existing test techniques. For instance, a test vector may need to be repeated many times to detect a fault. Also, different vectors detect the same fault with different probabilities. We develop test generation methods that account for these differences, and integer linear programming (ILP) formulations to optimize test sets.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/61584/1/smita_1.pd

Inductive Equivalence Checking and Relation Determinization via SAT Solving

在這篇論文的第一部份，我們著眼於驗證。時序重整與再生轉換是兩種重要的電路最佳化技術，但是由於驗證的困難，使得它們的應用受到了限制。如果能克服這瓶頸，相信他們的應用會更廣泛。我們針對時序重整與再生轉換的電路，研究他們在歸納式等同驗證方法中的完備條件。此外，以往的研究沒有同時考慮時序重整和再生轉換，他們只對其中一項技術的驗證有完備性。我們的方法，能到對一次時序重整，再做再生轉換，最後再做一次時序重整的電路有完備性。實驗結果顯示我們的方法可以應用在較大的電路上，我們也可以驗證之前研究無法解決的一些電路。二部份我們研究布林關係確定。很多硬體和軟體的合成問題都可以簡化成條件求解。而可行的解法是將這些條件是用布林關係來表示。但是這些關係並不能直接解決問題。除非關係是被決定而且可以轉換成相對應的函數，否則關係無法用電路來表示。我們運用內插法來求取關係的對應函數，這方法利用關係的彈性並且不需去考慮它的不相關項。The first part of this thesis focuses on verification. Retiming and resynthesis are both important techniques for sequential circuit optimization, but their applicability is limited because the verification is hard. Overcoming the verification bottleneck can enhance the practicality of retiming and resynthesis. We study the completeness condition of the inductive approach for equivalence checking under retiming and resynthesis. Besides, the prior work is only complete for circuits transformed under retiming or resynthesis, but not both. Our approach is complete for circuits transformed up to retiming+resynthesis+retiming. The experimental results show the capability and scalability of our approach. Several previously unverifiable instances can be verified effectively. he second part of this thesis studies the determinization of Boolean relations. Many problems in hardware and software synthesis can be reduced to constraint solving. The feasible solutions of such constraints are often in the form of Boolean relations. Boolean relations however are not directly useful. Unless a Boolean is determinized and transformed into a set of Boolean functions, it cannot be implemented as a circuit. We derive the functional implementation of a Boolean relation through SAT solving and Craig interpolation. The computation provides a way exploit flexibility without computing don''t care and is more scalable compared with prior BDD-based methods.Acknowledgements i 文摘要 ii bstract iii ist of Figures ix ist of Tables x Introduction 1 .1 Equivalence Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 .2 Relation Determinization . . . . . . . . . . . . . . . . . . . . . . . . . . 4 .3 Our Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 .4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 6 Preliminaries 7 .1 The Boolean Satisfiability Problem . . . . . . . . . . . . . . . . . . . . . 7 .1.1 Conjunctive Normal Form . . . . . . . . . . . . . . . . . . . . . 8 .1.2 SAT Solvers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 .2 Finite State Machines and The Product Machine . . . . . . . . . . . . . . 11 Inductive Equivalence Checking 12 .1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 .1.1 Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 12 .1.2 Retiming and Resynthesis . . . . . . . . . . . . . . . . . . . . . 13 .2 The Invariant and Signal Correspondence . . . . . . . . . . . . . . . . . 15 .2.1 Signal Correspondence . . . . . . . . . . . . . . . . . . . . . . . 16 .2.2 Theoretical Investigation . . . . . . . . . . . . . . . . . . . . . . 18 .3 Timeframe Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 .4 Equivalence Checking Methods . . . . . . . . . . . . . . . . . . . . . . 26 .4.1 Retiming Equivalence . . . . . . . . . . . . . . . . . . . . . . . 26 .4.2 Retiming+Resynthesis Equivalence . . . . . . . . . . . . . . . . 29 .4.3 Resynthesis+Retiming Equivalence . . . . . . . . . . . . . . . . 30 .4.4 Retiming+Resynthesis+Retiming Equivalence . . . . . . . . . . 30 .4.5 Resynthesis+Retiming+Resynthesis Equivalence and Beyond . . 32 .4.6 Practical Implementation . . . . . . . . . . . . . . . . . . . . . . 32 .5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Relation Determinization 44 .1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 .1.1 Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 .1.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 .1.3 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . 46 .2 Craig Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 .3 Single-Output Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 .3.1 Total Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 .3.2 Partial Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 .4 Multiple-Output Relation . . . . . . . . . . . . . . . . . . . . . . . . . . 54 .4.1 Substitution1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 .4.2 Substitution2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 .4.3 Duplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 .5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Conclusions and Future Work 68 ibliography 7