Testing for delay defects utilizing test data compression techniques

textAs technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.Electrical and Computer Engineerin

Pseudo-functional testing: bridging the gap between manufacturing test and functional operation.

Yuan, Feng.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references (leaves 60-65).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.iiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Manufacturing Test --- p.1Chapter 1.1.1 --- Functional Testing vs. Structural Testing --- p.2Chapter 1.1.2 --- Fault Model --- p.3Chapter 1.1.3 --- Automatic Test Pattern Generation --- p.4Chapter 1.1.4 --- Design for Testability --- p.6Chapter 1.2 --- Pseudo-Functional Manufacturing Test --- p.13Chapter 1.3 --- Thesis Motivation and Organization --- p.16Chapter 2 --- On Systematic Illegal State Identification --- p.19Chapter 2.1 --- Introduction --- p.19Chapter 2.2 --- Preliminaries and Motivation --- p.20Chapter 2.3 --- What is the Root Cause of Illegal States? --- p.22Chapter 2.4 --- Illegal State Identification Flow --- p.26Chapter 2.5 --- Justification Scheme Construction --- p.30Chapter 2.6 --- Experimental Results --- p.34Chapter 2.7 --- Conclusion --- p.35Chapter 3 --- Compression-Aware Pseudo-Functional Testing --- p.36Chapter 3.1 --- Introduction --- p.36Chapter 3.2 --- Motivation --- p.38Chapter 3.3 --- Proposed Methodology --- p.40Chapter 3.4 --- Pattern Generation in Compression-Aware Pseudo-Functional Testing --- p.42Chapter 3.4.1 --- Circuit Pre-Processing --- p.42Chapter 3.4.2 --- Pseudo-Functional Random Pattern Generation with Multi-Launch Cycles --- p.43Chapter 3.4.3 --- Compressible Test Pattern Generation for Pseudo-Functional Testing --- p.45Chapter 3.5 --- Experimental Results --- p.52Chapter 3.5.1 --- Experimental Setup --- p.52Chapter 3.5.2 --- Results and Discussion --- p.54Chapter 3.6 --- Conclusion --- p.56Chapter 4 --- Conclusion and Future Work --- p.58Bibliography --- p.6

Fehlercharakterisierung zuverlässiger Schaltungen im Selbsttest

Hochintegrierte Schaltungen können immer kleiner, höher getaktet und energieeffizienter hergestellt werden, allerdings können bedingt durch diese technologischen Trends auch vermehrt Schwachstellen im System entstehen. Diese Schwachstellen führen oft während des Produktionstests nicht zu einem Fehlverhalten der Schaltung, während des Betriebs allerdings droht durch die steigende Anfälligkeit gegenüber intrinsischen und äußeren Störeinflüssen sowie Alterungseffekten ein vorzeitiger Ausfall der Schaltung. Solche Frühausfälle werden „Early-Life Fehler“ genannt und können mit einem Standard- Test ohne weitere Anpassungen nicht erkannt werden. Indikatoren für einen Frühausfall können intermittierende Fehler, aber auch kleine Verzögerungsfehler sein. In dieser Arbeit wird ein Selbsttest vorgestellt, der eine Fehlercharakterisierung zur Erkennung von Systemschwachstellen und Vermeidung von Frühausfällen, speziell solche, die sich als intermittierender Fehler oder kleiner Verzögerungsfehler auswirken, mit geringem Hardware- und Zeitaufwand mittels eines Standard-Tests ermöglicht. Hierzu wird im Selbsttest zunächst zwischen permanenten und nicht-permanenten Fehlern unterschieden und eine Klassifikation der nicht- permanenten Fehler mit Hilfe eines voran geschalteten Diagnoseverfahrens und Bayesschen Berechnungen durchgeführt. Hierdurch lässt sich die Produktqualität ohne zusätzliche Ausbeuteverluste erhöhen. Zusätzlich wird ein Test mit erhöhter Betriebsfrequenz vorgestellt, der im Selbsttest kleine Verzögerungsfehler erkennt.As a result of the fact, that todays integrated circuits have smaller features sizes, higher frequencies and are more energy efficient, weak spots can occur in the system. These weak spots can be undetected by the production test, but during system operation they can lead to hard failures, because of increasing susceptibility to intrinsic and external disturbances or aging effects. This early system breakdown is called „early-life failure“ and cannot be detected by a standard test without any adjustments. Indicators of early-life failures could be intermittent faults and also small delay defects. In this thesis a built-in self-test is presented, which characterizes faulty behavior to detect weak spots and avoid early-life failures, especially caused by intermittent faults or small delay defects, with low hardware and time overhead by using a standard test set. In a first step, the test procedure can distinguish between permanent and non-permanent faults. After that, a diagnosis process and Bayesian reasoning implement the classification of the non-permanent faults. With this procedure the product quality can be increased without additional yield loss. Furthermore a Faster-than-at-Speed-Test (FAST) will be introduced, which allows detecting SDDs in a built-in self-test environment without any changes in the ATPG flow.von Dipl.-Wirt.-Ing. Thomas Indlekofer ; Erster Gutachter: Prof. Dr. Sybille Hellebrand, Zweiter Gutachter: Prof. Dr. Ilia PolianTag der Verteidigung: 03.03.2016Fakultät für Elektrotechnik, Informatik und Mathematik der Universität Paderborn, Univ., Dissertation, 201

Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation

Recently, an X-canceling MISR methodology was proposed in [Touba 07] which was based on providing very high probabilistic error coverage by canceling out X's in MISR signatures. This paper investigates a new methodology for using the X-canceling MISR architecture based on deterministically observing scan cells. The two main advantages of the proposed approach are (1) it can provide a higher amount of compaction, and (2) it is effective for larger percentages of X's in the output response. Also, this paper investigates a hybrid approach that combines X-masking with an X-canceling MISR. Experimental results indicate that significant amounts of output compression can be achieved with no loss of fault coverage