Power Estimation Technique for DSP Architectures.

The main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modeling technique for digital signal processing (DSP) architectures in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate power dissipation of the system just by using the statistics of the macro-block’s primary in puts. In experiments with the DSP system, the average error is 26%

INCORPORATION OF INPUT GLITCHES INTO POWER MACROMODELING

xunliu,marios¡ Previous research on power macromodeling has always assumed glitch-free input signals. However, in an actual operating environment, the input signals of a circuit can contain glitches, which are generated by the previous stage of circuitry. In this paper, we investigate the impact of input glitches on the power dissipation of a circuit. Specifically, we show that the frequency and average duration of input glitches are two important factors affecting the overall power consumption. Input glitches can also increase output glitching by a surprisingly large amount. We present a simple yet effective analytical power macromodeling approach incorporating the effects of input glitching. In experiments with the ISCAS-85 benchmark circuits, the average error of the proposed technique is 4.44%. 1