Time Multiplexed Active Neural Probe with 678 Parallel Recording Sites

We present a high density CMOS neural probe with active electrodes (pixels), consisting of dedicated in-situ circuits for signal source amplification. The complete probe contains 1356 neuron size (20x20 μm2) pixels densely packed on a 50 μm thick, 100 μm wide and 8 mm long shank. It allows simultaneous highperformance recording from 678 electrodes and a possibility to simultaneously observe all of the 1356 electrodes with increased noise. This considerably surpasses the state of the art active neural probes in electrode count and flexibility. The measured action potential band noise is 12.4 μVrms, with just 3 μW power dissipation per electrode amplifier and 45 μW per channel (including data transmission)

Time Multiplexed Active Neural Probe with 1356 Parallel Recording Sites

We present a high electrode density and high channel count CMOS (complementary metal-oxide-semiconductor) active neural probe containing 1344 neuron sized recording pixels (20 µm × 20 µm) and 12 reference pixels (20 µm × 80 µm), densely packed on a 50 µm thick, 100 µm wide, and 8 mm long shank. The active electrodes or pixels consist of dedicated in-situ circuits for signal source amplification, which are directly located under each electrode. The probe supports the simultaneous recording of all 1356 electrodes with sufficient signal to noise ratio for typical neuroscience applications. For enhanced performance, further noise reduction can be achieved while using half of the electrodes (678). Both of these numbers considerably surpass the state-of-the art active neural probes in both electrode count and number of recording channels. The measured input referred noise in the action potential band is 12.4 µVrms, while using 678 electrodes, with just 3 µW power dissipation per pixel and 45 µW per read-out channel (including data transmission)

Advancing the interfacing performances of chronically implantable neural probes in the era of CMOS neuroelectronics

Tissue penetrating microelectrode neural probes can record electrophysiological brain signals at resolutions down to single neurons, making them invaluable tools for neuroscience research and Brain-Computer-Interfaces (BCIs). The known gradual decrease of their electrical interfacing performances in chronic settings, however, remains a major challenge. A key factor leading to such decay is Foreign Body Reaction (FBR), which is the cascade of biological responses that occurs in the brain in the presence of a tissue damaging artificial device. Interestingly, the recent adoption of Complementary Metal Oxide Semiconductor (CMOS) technology to realize implantable neural probes capable of monitoring hundreds to thousands of neurons simultaneously, may open new opportunities to face the FBR challenge. Indeed, this shift from passive Micro Electro-Mechanical Systems (MEMS) to active CMOS neural probe technologies creates important, yet unexplored, opportunities to tune probe features such as the mechanical properties of the probe, its layout, size, and surface physicochemical properties, to minimize tissue damage and consequently FBR. Here, we will first review relevant literature on FBR to provide a better understanding of the processes and sources underlying this tissue response. Methods to assess FBR will be described, including conventional approaches based on the imaging of biomarkers, and more recent transcriptomics technologies. Then, we will consider emerging opportunities offered by the features of CMOS probes. Finally, we will describe a prototypical neural probe that may meet the needs for advancing clinical BCIs, and we propose axial insertion force as a potential metric to assess the influence of probe features on acute tissue damage and to control the implantation procedure to minimize iatrogenic injury and subsequent FBR

Automatic Tuning of Digital Circuits.

Variation in transistors is increasing as process technology transistor dimensions shrink. Compounded with lowering supply voltage, this increased variation presents new challenges for the circuit designer. However, this variation also brings many new opportunities for the circuit designer to leverage as well. We present a time-to-digital converter embedded inside a 64-bit processor core, for direct monitoring of on-chip critical paths. This path monitoring allows the processor to monitor process variation and run-time variations. By adjusting to both static and dynamic operating conditions the impact of variations can be reduced. The time-to-digital converter achieves high-resolution measurement in the picosecond range, due to self-calibration via a self-feedback mode. This system is implemented in 45nm silicon and measured silicon results are shown. We also examine techniques for enhanced variation-tolerance in subthreshold digital circuits, applying these to a high fan-in, self-timed transition detection circuit that, due to its self-timing, is able to fully compensate for the large variation in subthreshold. In addition to mitigating variations we also leverage them for random number generation. We demonstrate that the randomness inherent in the oxide breakdown process can be extracted and applied for the specific applications of on-chip ID generation and on-chip true random number generation. By using dynamic automated self-calibrating algorithms that tune and control the on-chip circuitry, we are able to achieve extremely high-quality results. The two systems are implemented in 65 nm silicon. Measured results for the on-chip ID system, called OxID, show a high-degree of randomness and read-stability in the generated IDs, both primary prerequisites of a high-quality on-chip ID system. Measured results for the true random number generator, called OxiGen, show an exceptionally high degree of randomness, passing all fifteen NIST 800-22 tests for randomness with statistical significance and without the aid of a post-processor.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86390/1/rachliu_1.pd

Characterization and mitigation of process variation in digital circuits and systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 155-166).Process variation threatens to negate a whole generation of scaling in advanced process technologies due to performance and power spreads of greater than 30-50%. Mitigating this impact requires a thorough understanding of the variation sources, magnitudes and spatial components at the device, circuit and architectural levels. This thesis explores the impacts of variation at each of these levels and evaluates techniques to alleviate them in the context of digital circuits and systems. At the device level, we propose isolation and measurement of variation in the intrinsic threshold voltage of a MOSFET using sub-threshold leakage currents. Analysis of the measured data, from a test-chip implemented on a 0. 18[mu]m CMOS process, indicates that variation in MOSFET threshold voltage is a truly random process dependent only on device dimensions. Further decomposition of the observed variation reveals no systematic within-die variation components nor any spatial correlation. A second test-chip capable of characterizing spatial variation in digital circuits is developed and implemented in a 90nm triple-well CMOS process. Measured variation results show that the within-die component of variation is small at high voltages but is an increasing fraction of the total variation as power-supply voltage decreases. Once again, the data shows no evidence of within-die spatial correlation and only weak systematic components. Evaluation of adaptive body-biasing and voltage scaling as variation mitigation techniques proves voltage scaling is more effective in performance modification with reduced impact to idle power compared to body-biasing.(cont.) Finally, the addition of power-supply voltages in a massively parallel multicore processor is explored to reduce the energy required to cope with process variation. An analytic optimization framework is developed and analyzed; using a custom simulation methodology, total energy of a hypothetical 1K-core processor based on the RAW core is reduced by 6-16% with the addition of only a single voltage. Analysis of yield versus required energy demonstrates that a combination of disabling poor-performing cores and additional power-supply voltages results in an optimal trade-off between performance and energy.by Nigel Anthony Drego.Ph.D

Time multiplexed active neural probe with 678 parallel recording sites

We present a high density CMOS neural probe with active electrodes (pixels), consisting of dedicated in-situ circuits for signal source amplification. The complete probe contains 1356 neuron sized (20×20 μm2) pixels densely packed on a 50 μm thick, 100 μm wide and 8 mm long shank. It allows simultaneous high-performance recording from 678 electrodes and a possibility to simultaneously observe all of the 1356 electrodes with increased noise. This considerably surpasses the state of the art active neural probes in electrode count and flexibility. The measured action potential band noise is 12.4 μVrms, with just 3 μW power dissipation per electrode amplifier and 45 μW per channel (including data transmission)

Characterization of an experimental ferrite LTCC tape system for microwave and millimeter-wave applications

An experimental-low temperature cofired ceramic (LTCC) ferrite tape system is characterized using circuits that are fabricated from the very material under test. Such in situ circuits provide data that are thought to be more representative of the performance obtainable by more complicated circuitry that will eventually be made from the same material using the same fabrication method. Emphasis is placed on simple measurements that can be performed using a minimum amount of equipment. For the first time, a compact in situ LTCC solenoid transformer is used to measure the magnetostatic properties of the ferrite, yielding a measured saturation flux density of 230 mT, a remanence of 136 mT, and a coercivity of 688 A/m. The peak linear relative permeability of the ferrite is 97 and its Curie temperature is low, only 117 °C. A novel two-port line-connected ring resonator is used to characterize the material in the 6-40 GHz range. At frequencies above 20 GHz, the relative permittivity of the ferrite is 11.0, whereas its loss tangent ranges from 0.002 to 0.004, demonstrating the ferrite's suitability for use in microwave and millimeter-wave circuitry