Enabling Reliable, Efficient, and Secure Computing for Energy Harvesting Powered IoT Devices

Energy harvesting is one of the most promising techniques to power devices for future generation IoT. While energy harvesting does not have longevity, safety, and recharging concerns like traditional batteries, its instability brings a new challenge to the embedded systems: the energy harvested from environment is usually weak and intermittent. With traditional CMOS based technology, whenever the power is off, the computation has to start from the very beginning. Compared with existing CMOS based memory devices, emerging non-volatile memory devices such as PCM and STT-RAM, have the benefits of sustaining the data even when there is no power. By checkpointing the processor's volatile state to non-volatile memory, a program can resume its execution immediately after power comes back on again instead of restarting from the very beginning with checkpointing techniques. However, checkpointing is not sufficient for energy harvesting systems. First, the program execution resumed from the last checkpoint might not execute correctly and causes inconsistency problem to the system. This problem is due to the inconsistency between volatile system state and non-volatile system state during checkpointing. Second, the process of checkpointing consumes a considerable amount of energy and time due to the slow and energy-consuming write operation of non-volatile memory. Finally, connecting to the internet poses many security issues to energy harvesting IoT devices. Traditional data encryption methods are both energy and time consuming which do not fit the resource constrained IoT devices. Therefore, a light-weight encryption method is in urgent need for securing IoT devices. Targeting those three challenges, this dissertation proposes three techniques to enable reliable, efficient, and secure computing in energy harvesting IoT devices. First, a consistency-aware checkpointing technique is proposed to avoid inconsistency errors generated from the inconsistency between volatile state and non-volatile state. Second, checkpoint aware hybrid cache architecture is proposed to guarantee reliable checkpointing while maintaining a low checkpointing overhead from cache. Finally, to ensure the security of energy harvesting IoT devices, an energy-efficient in-memory encryption implementation for protecting the IoT device is proposed which can quickly encrypts the data in non-volatile memory and protect the embedded system physical and on-line attacks

Design Space Exploration and Resource Management of Multi/Many-Core Systems

The increasing demand of processing a higher number of applications and related data on computing platforms has resulted in reliance on multi-/many-core chips as they facilitate parallel processing. However, there is a desire for these platforms to be energy-efficient and reliable, and they need to perform secure computations for the interest of the whole community. This book provides perspectives on the aforementioned aspects from leading researchers in terms of state-of-the-art contributions and upcoming trends

MODELING AND BENCHMARKING OF SPINTRONIC DEVICES AND THEIR APPLICATIONS

Spintronic devices are promising candidates for low power applications such as logic and memory due to the characteristics of non-volatility, scalability, and fast switching speed. To evaluate the array-level performances of various spintronic memory devices, we have benchmarked spin-transfer torque magnetorestrictive random-access memory (STT-MRAM), spin-orbit torque MRAM (SOT-MRAM), voltage-controlled exchange coupling MRAM (VCEC-MRAM), and magnetoelectric MRAM (ME-MRAM). Among them, electric-field driven devices such as magnetoelectric (ME) device and the VCEC-MRAM can eliminate the joule heating energy thus is potentially more energy efficient than the current-controlled devices. Bismuth ferrite (BiFeO3) is a multiferroic material with the properties of ferroelectricity, antiferromagnetism, and weak ferromagnetism at room temperature. By combining BiFeO3 with a ferromagnet such as CoFe to form a BiFeO3/CoFe heterojunction, one can manipulate the magnetic state of CoFe by applying an external electric field. However, the switching mechanisms of the ferroelectric and the magnetic order of the BiFeO3 and CoFe are less understood which limits the estimation of the delay time and the write energy of the ME device. To evaluate the potential performance of this voltage-controlled BFO/CoFe heterojunction device in memory or logic application, we present a unified micromagnetic/ferroelectric simulation framework that can model the transient response and the switching behaviors of both BFO and CoFe layers. In addition, the important material parameters such as the interface exchange coupling coefficient are extracted from the experiments. Next, we build a physics-based compact model of the BFO/CoFe heterojunction to simulate the ME device in the circuit level. The results from our compact model closely match very well with those from the micromagnetic models when simulating the magnetization dynamics of BFO and CoFe. Using the compact model we developed, the SPICE simulation shows that ME-MRAM can potentially operate with a lower write energy compared to the STT-MRAM, SOT-MRAM or even SRAM when the coercive voltage of the BFO layer is as small as 20mV. Last, we model and benchmark the read and write performances of SOT-MRAM using various SOT materials including heavy metals, alloys, Weyl semi-metals, and topological insulators. The non-ideal factors such as current-shunting effect, current crowding effect, and the variability are included. Our results indicate that spintronic memory devices are prospective candidates in the embedded memory application due to the better energy efficiency and smaller layout area compared to SRAM.Ph.D

In-Memory Computing With Spintronic Devices

In-Memory computing has drawn many attentions as a promising solution to reduce massive power hungry data traffic between computing and memory units, leading to significant improvement of entire system performance and energy efficiency. Emerging spintronic device based non-volatile memory is becoming a next-generation universal memory candidate due to its non-volatility, zero leakage power in un-accessed bit-cell, high integration density, excellent endurance and compatibility with CMOS fabrication technology. In this paper, we present that different spintronic devices based memory, including spin-orbit torque magnetic random access memory (SOT-MRAM), domain wall motion memory, magnetic racetrack memory, could be leveraged to implement logic functions within memory without add-on logic circuits. As a case study, we employ Advanced Encryption Standard (AES) algorithm to elucidate the efficiency of such in-memory computing based on spintronic memory