Design and implementation of the embedded capacitance layers for decoupling of wireless sensor nodes

In this paper, the embedded capacitance material (ECM) is fabricated between the power and ground layers of the wireless sensor nodes, forming an integrated capacitance to replace the large amount of decoupling capacitors on the board. The ECM material, whose dielectric constant is 16, has the same size of the wireless sensor nodes of 3cm*3cm, with a thickness of only 14μm. Though the capacitance of a single ECM layer being only around 8nF, there are two reasons the ECM layers can still replace the high frequency decoupling capacitors (100nF in our case) on the board. The first reason is: the parasitic inductance of the ECM layer is much lower than the surface mount capacitors'. A smaller capacitance value of the ECM layer could achieve the same resonant frequency of the surface mount decoupling capacitors. Simulation and measurement fit this assumption well. The second reason is: more than one layer of ECM material are utilized during the design step to get a parallel connection of the several ECM capacitance layers, finally leading to a larger value of the capacitance and smaller value of parasitic. Characterization of the ECM is carried out by the LCR meter. To evaluate the behaviors of the ECM layer, time and frequency domain measurements are performed on the power-bus decoupling of the wireless sensor nodes. Comparison with the measurements of bare PCB board and decoupling capacitors solution are provided to show the improvement of the ECM layer. Measurements show that the implementation of the ECM layer can not only save the space of the surface mount decoupling capacitors, but also provide better power-bus decoupling to the nodes

Dynamic range optimisation of CMOS image sensors dedicated to space applications

Nowadays, CMOS image sensors are widely considered for space applications. Their performances have been significantly enhanced with the use of CIS (CMOS Image Sensor) processes in term of dark current, quantum efficiency and conversion gain. Dynamic Range (DR) remains an important parameter for a lot of applications. Most of the dynamic range limitation of CMOS image sensors comes from the pixel. During work performed in collaboration with EADS Astrium, SUPAERO/CIMI laboratory has studied different ways to improve dynamic range and test structures have been developed to perform analysis and characterisation. A first way to improve dynamic range will be described, consisting in improving the voltage swing at the pixel output. Test vehicles and process modifications made to improve voltage swing will be depicted. We have demonstrated a voltage swing improvement more than 30%. A second way to improve dynamic range is to reduce readout noise A new readout architecture has been developed to perform a correlated double sampling readout. Strong readout noise reduction will be demonstrated by measurements performed on our test vehicle. A third way to improve dynamic range is to control conversion gain value. Indeed, in 3 TMOS pixel structure, dynamic range is related to conversion gain through reset noise which is dependant of photodiode capacitance. Decrease and increase of conversion gain have been performed with different design techniques. A good control of the conversion gain will be demonstrated with variation in the range of 0.05 to 3 of initial conversion gain

A new lab-on-chip transmitter for the detection of proteins using RNA aptamers

A new RNA aptamer based affinity biosensor for CReactive Protein (CRP), a risk marker for cardiovascular disease was developed using interdigitated capacitor (IDC), integrated in Voltage Controlled Oscillator (VCO) and output signal is amplified using Single Stage Power Amplifier (PA) for transmitting signal to receiver at Industrial, Scientific and Medical (ISM) band. The Lab-on-Chip transmitter design includes IDC, VCO and PA. The design was implemented in IHP 0.25μm SiGe BiCMOS process; post-CMOS process was utilized to increase the sensitivity of biosensor. The CRP was incubated between or on interdigitated electrodes and the changes in capacitance of IDC occurred. In blank measurements, the oscillation frequency was 2.464GHz whereas after RNA aptamers were immobilized on open aluminum areas of IDC and followed by binding reaction processed with 500pg/ml CRP solution, the capacitance shifted to 2.428GHz. Phase noise is changed from -114.3dBc/Hz to -116.5dBc/Hz

A power-saving modulation technique for time-of-flight range imaging sensors

Time-of-flight range imaging cameras measure distance and intensity simultaneously for every pixel in an image. With the continued advancement of the technology, a wide variety of new depth sensing applications are emerging; however a number of these potential applications have stringent electrical power constraints that are difficult to meet with the current state-of-the-art systems. Sensor gain modulation contributes a significant proportion of the total image sensor power consumption, and as higher spatial resolution range image sensors operating at higher modulation frequencies (to achieve better measurement precision) are developed, this proportion is likely to increase. The authors have developed a new sensor modulation technique using resonant circuit concepts that is more power efficient than the standard mode of operation. With a proof of principle system, a 93–96% reduction in modulation drive power was demonstrated across a range of modulation frequencies from 1–11 MHz. Finally, an evaluation of the range imaging performance revealed an improvement in measurement linearity in the resonant configuration due primarily to the more sinusoidal shape of the resonant electrical waveforms, while the average precision values were comparable between the standard and resonant operating modes

Rapid state purification protocols for a Cooper pair box

We propose techniques for implementing two different rapid state purification schemes, within the constraints present in a superconducting charge qubit system. Both schemes use a continuous measurement of charge (z) measurements, and seek to minimize the time required to purify the conditional state. Our methods are designed to make the purification process relatively insensitive to rotations about the x-axis, due to the Josephson tunnelling Hamiltonian. The first proposed method, based on the scheme of Jacobs [Phys. Rev. A 67, 030301(R) (2003)] uses the measurement results to control bias (z) pulses so as to rotate the Bloch vector onto the x-axis of the Bloch sphere. The second proposed method, based on the scheme of Wiseman and Ralph [New J. Phys. 8, 90 (2006)] uses a simple feedback protocol which tightly rotates the Bloch vector about an axis almost parallel with the measurement axis. We compare the performance of these and other techniques by a number of different measures.Comment: 14 pages, 14 figures. v2: Revised version after referee comments. Accepted for publication by Physical Review

CMOS detectors for space applications: from R&D to operational program with large volume foundry

Nowadays, CMOS image sensors are widely considered for space applications. The use of CIS (CMOS Image sensor) processes has significantly enhanced their performances such as dark current, quantum efficiency and conversion gain. However, in order to fulfil specific space mission requirements, dedicated research and development work has to be performed to address specific detector performance issues. This is especially the case for dynamic range improvement through output voltage swing optimisation, control of conversion gain and noise reduction. These issues have been addressed in a 0.35μm CIS process, based on a large volume CMOS foundry, by several joint ISAE- EADS Astrium R&D programs. These results have been applied to the development of the visible and near-infrared multi-linear imager for the SENTINEL 2 mission (LEO Earth observation mission for the Global Measurement Environment and Security program). For this high performance multi-linear device, output voltage swing improvement is achieved by process optimisation done in collaboration with foundry. Conversion gain control is also achieved for each spectral band by managing photodiode capacitance. A low noise level at sensor output is reached by the use of an architecture allowing Correlated Double Sampling readout in order to eliminate reset noise (KTC noise). KTC noise elimination reveals noisy pixels due to RTS noise. Optimisation of transistors’s dimensions, taking into account conversion gain constraints, is done to minimise these noisy pixels. Additional features have been also designed: 1) Due to different integration times between spectral bands required by mission, a specific readout mode was developed in order to avoid electrical perturbations during the integration time and readout. This readout mode leads to specific power supply architecture. 2)Post processing steps can be achieved by alignment marks design allowing a very good accuracy. These alignment marks can be used for a black coating deposition between spectral bands (pixel line) in order to minimise straight lighteffects. In conclusion a review of design improvements and performances of the final component is performed

A Pixel Vertex Tracker for the TESLA Detector

In order to fully exploit the physics potential of a e+e- linear collider, such as TESLA, a Vertex Tracker providing high resolution track reconstruction is required. Hybrid Silicon pixel sensors are an attractive sensor technology option due to their read-out speed and radiation hardness, favoured in the high rate TESLA environment, but have been so far limited by the achievable single point space resolution. A novel layout of pixel detectors with interleaved cells to improve their spatial resolution is introduced and the results of the characterisation of a first set of test structures are discussed. In this note, a conceptual design of the TESLA Vertex Tracker, based on hybrid pixel sensors is presentedComment: 20 pages, 11 figure

Cancellation of crosstalk-induced jitter

A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10^sup-12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps