145 research outputs found
Memristive Computing
Memristive computing refers to the utilization of the memristor, the fourth
fundamental passive circuit element, in computational tasks.
The existence of the memristor was theoretically predicted in 1971 by
Leon O. Chua, but experimentally validated only in 2008 by HP Labs. A
memristor is essentially a nonvolatile nanoscale programmable resistor —
indeed, memory resistor — whose resistance, or memristance to be precise,
is changed by applying a voltage across, or current through, the device.
Memristive computing is a new area of research, and many of its fundamental
questions still remain open. For example, it is yet unclear which
applications would benefit the most from the inherent nonlinear dynamics
of memristors. In any case, these dynamics should be exploited to allow
memristors to perform computation in a natural way instead of attempting
to emulate existing technologies such as CMOS logic. Examples of such
methods of computation presented in this thesis are memristive stateful logic
operations, memristive multiplication based on the translinear principle, and
the exploitation of nonlinear dynamics to construct chaotic memristive circuits.
This thesis considers memristive computing at various levels of abstraction.
The first part of the thesis analyses the physical properties and the
current-voltage behaviour of a single device. The middle part presents memristor
programming methods, and describes microcircuits for logic and analog
operations. The final chapters discuss memristive computing in largescale
applications. In particular, cellular neural networks, and associative
memory architectures are proposed as applications that significantly benefit
from memristive implementation. The work presents several new results on
memristor modeling and programming, memristive logic, analog arithmetic
operations on memristors, and applications of memristors.
The main conclusion of this thesis is that memristive computing will
be advantageous in large-scale, highly parallel mixed-mode processing architectures.
This can be justified by the following two arguments. First,
since processing can be performed directly within memristive memory architectures,
the required circuitry, processing time, and possibly also power
consumption can be reduced compared to a conventional CMOS implementation.
Second, intrachip communication can be naturally implemented by
a memristive crossbar structure.Siirretty Doriast
Memristor-Based Digital Systems Design and Architectures
Memristor is considered as a suitable alternative solution to resolve the scaling limitation of CMOS technology. In recent years, the use of memristors in circuits design has rapidly increased and attracted researcher’s interest. Advances have been made to both size and complexity of memristor designs. The development of CMOS transistors shows major concerns, such as, increased leakage power, reduced reliability, and high fabrication cost. These factors have affected chip manufacturing process and functionality severely. Therefore, the demand for new devices is increasing. Memristor, is considered as one of the key element in memory and information processing design due to its small size, long-term data storage, low power, and CMOS compatibility. The main objective in this research is to design memristor-based arithmetic circuits and to overcome some of the Memristor based logic design issues. In this thesis, a fast, low area and low power hybrid CMOS memristor based digital circuit design were implemented. Small and large-scale memristor based digital circuits are implemented and provided a solutions for overcoming the memristor degradation and fan-out challenges. As an example, a 4- bit LFSR has been implemented by using MRL scheme with 64 CMOS devices and 64 memristors. The proposed design is more efficient in terms of the area when compared with CMOS- based LFSR circuits. The simulation results proves the functionality of the design. This approach presents acceptable speed in comparison with CMOS-based design and it is faster than IMPLY-based memrisitive LFSR. The propped LFSR has 841 ps de-lay. Furthermore, the proposed design has a significant power reduction of over 66% less than CMOS-based approach. This thesis proposes implementation of memristive 2-D median filter and extends previously published works on memristive Filter design to include this emerging technology characteristics in image processing. The proposed circuit was designed based on Pt/TaOx/Ta redox-based device and Memristor Ratioed Logic (MRL). The proposed filter is designed in Cadence and the memristive median approved tested circuit is translated to Verilog-XL as a behavioral model. Different 512 _ 512 pixels input images contain salt and pepper noise with various noise density ratios are applied to the proposed median filter and the design successfully has substantially removed the noise. The implementation results in comparison with the conventional filters, it gives better Peak Signal to Noise Ratio (PSNR) and Mean Absolute Error (MAE) for different images with different noise density ratios while it saves more area as compared to CMOS-based design. This dissertation proposes a comprehensive framework for design, mapping and synthesis of large-scale memristor-CMOS circuits. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library for large scale simulation. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was veri_ed with Verilog-XL, MATLAB, and the Electronic Design Automation (EDA) Synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. The frame work is deployed for design of the memristor-based parallel 8-bit adder/subtractor and a 2-D memristive-based median filter
Computers from plants we never made. Speculations
We discuss possible designs and prototypes of computing systems that could be
based on morphological development of roots, interaction of roots, and analog
electrical computation with plants, and plant-derived electronic components. In
morphological plant processors data are represented by initial configuration of
roots and configurations of sources of attractants and repellents; results of
computation are represented by topology of the roots' network. Computation is
implemented by the roots following gradients of attractants and repellents, as
well as interacting with each other. Problems solvable by plant roots, in
principle, include shortest-path, minimum spanning tree, Voronoi diagram,
-shapes, convex subdivision of concave polygons. Electrical properties
of plants can be modified by loading the plants with functional nanoparticles
or coating parts of plants of conductive polymers. Thus, we are in position to
make living variable resistors, capacitors, operational amplifiers,
multipliers, potentiometers and fixed-function generators. The electrically
modified plants can implement summation, integration with respect to time,
inversion, multiplication, exponentiation, logarithm, division. Mathematical
and engineering problems to be solved can be represented in plant root networks
of resistive or reaction elements. Developments in plant-based computing
architectures will trigger emergence of a unique community of biologists,
electronic engineering and computer scientists working together to produce
living electronic devices which future green computers will be made of.Comment: The chapter will be published in "Inspired by Nature. Computing
inspired by physics, chemistry and biology. Essays presented to Julian Miller
on the occasion of his 60th birthday", Editors: Susan Stepney and Andrew
Adamatzky (Springer, 2017
Optimized Implementation of Memristor-Based Full Adder by Material Implication Logic
Recently memristor-based applications and circuits are receiving an increased
attention. Furthermore, memristors are also applied in logic circuit design.
Material implication logic is one of the main areas with memristors. In this
paper an optimized memristor-based full adder design by material implication
logic is presented. This design needs 27 memristors and less area in comparison
with typical CMOS-based 8-bit full adders. Also the presented full adder needs
only 184 computational steps which enhance former full adder design speed by 20
percent.Comment: International Conference on Electronics Circuits and Systems (ICECS),
201
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