Resonate and Fire Neuron with Fixed Magnetic Skyrmions

In the brain, the membrane potential of many neurons oscillates in a subthreshold damped fashion and fire when excited by an input frequency that nearly equals their eigen frequency. In this work, we investigate theoretically the artificial implementation of such "resonate-and-fire" neurons by utilizing the magnetization dynamics of a fixed magnetic skyrmion in the free layer of a magnetic tunnel junction (MTJ). To realize firing of this nanomagnetic implementation of an artificial neuron, we propose to employ voltage control of magnetic anisotropy or voltage generated strain as an input (spike or sinusoidal) signal, which modulates the perpendicular magnetic anisotropy (PMA). This results in continual expansion and shrinking (i.e. breathing) of a skyrmion core that mimics the subthreshold oscillation. Any subsequent input pulse having an interval close to the breathing period or a sinusoidal input close to the eigen frequency drives the magnetization dynamics of the fixed skyrmion in a resonant manner. The time varying electrical resistance of the MTJ layer due to this resonant oscillation of the skyrmion core is used to drive a Complementary Metal Oxide Semiconductor (CMOS) buffer circuit, which produces spike outputs. By rigorous micromagnetic simulation, we investigate the interspike timing dependence and response to different excitatory and inhibitory incoming input pulses. Finally, we show that such resonate and fire neurons have potential application in coupled nanomagnetic oscillator based associative memory arrays

Evaluating local indirect addressing in SIMD proc essors

In the design of parallel computers, there exists a tradeoff between the number and power of individual processors. The single instruction stream, multiple data stream (SIMD) model of parallel computers lies at one extreme of the resulting spectrum. The available hardware resources are devoted to creating the largest possible number of processors, and consequently each individual processor must use the fewest possible resources. Disagreement exists as to whether SIMD processors should be able to generate addresses individually into their local data memory, or all processors should access the same address. The tradeoff is examined between the increased capability and the reduced number of processors that occurs in this single instruction stream, multiple, locally addressed, data (SIMLAD) model. Factors are assembled that affect this design choice, and the SIMLAD model is compared with the bare SIMD and the MIMD models

Time-predictable Chip-Multiprocessor Design

Abstract—Real-time systems need time-predictable platforms to enable static worst-case execution time (WCET) analysis. Improving the processor performance with superscalar techniques makes static WCET analysis practically impossible. However, most real-time systems are multi-threaded applications and performance can be improved by using several processor cores on a single chip. In this paper we present a time-predictable chipmultiprocessor system that aims to improve system performance while still enabling WCET analysis. The proposed chip-multiprocessor (CMP) uses a shared memory with a time-division multiple access (TDMA) based memory access scheduling. The static TDMA schedule can be integrated into the WCET analysis. Experiments with a JOP based CMP showed that the memory access starts to dominate the execution time when using more than 4 processor cores. To provide a better scalability, more local memories have to be used. We add a processor local scratchpad memory and split data caches, which are still time-predictable, to the processor cores. I

A Verified Information-Flow Architecture

SAFE is a clean-slate design for a highly secure computer system, with pervasive mechanisms for tracking and limiting information flows. At the lowest level, the SAFE hardware supports fine-grained programmable tags, with efficient and flexible propagation and combination of tags as instructions are executed. The operating system virtualizes these generic facilities to present an information-flow abstract machine that allows user programs to label sensitive data with rich confidentiality policies. We present a formal, machine-checked model of the key hardware and software mechanisms used to dynamically control information flow in SAFE and an end-to-end proof of noninterference for this model. We use a refinement proof methodology to propagate the noninterference property of the abstract machine down to the concrete machine level. We use an intermediate layer in the refinement chain that factors out the details of the information-flow control policy and devise a code generator for compiling such information-flow policies into low-level monitor code. Finally, we verify the correctness of this generator using a dedicated Hoare logic that abstracts from low-level machine instructions into a reusable set of verified structured code generators