11 research outputs found
Implementing Bayesian Networks with Embedded Stochastic MRAM
Magnetic tunnel junctions (MTJ's) with low barrier magnets have been used to
implement random number generators (RNG's) and it has recently been shown that
such an MTJ connected to the drain of a conventional transistor provides a
three-terminal tunable RNG or a -bit. In this letter we show how this
-bit can be used to build a -circuit that emulates a Bayesian network
(BN), such that the correlations in real world variables can be obtained from
electrical measurements on the corresponding circuit nodes. The -circuit
design proceeds in two steps: the BN is first translated into a behavioral
model, called Probabilistic Spin Logic (PSL), defined by dimensionless biasing
(h) and interconnection (J) coefficients, which are then translated into
electronic circuit elements. As a benchmark example, we mimic a family tree of
three generations and show that the genetic relatedness calculated from a
SPICE-compatible circuit simulator matches well-known results
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations
Bayesian Neural Networks (BayNNs) naturally provide uncertainty in their
predictions, making them a suitable choice in safety-critical applications.
Additionally, their realization using memristor-based in-memory computing (IMC)
architectures enables them for resource-constrained edge applications. In
addition to predictive uncertainty, however, the ability to be inherently
robust to noise in computation is also essential to ensure functional safety.
In particular, memristor-based IMCs are susceptible to various sources of
non-idealities such as manufacturing and runtime variations, drift, and
failure, which can significantly reduce inference accuracy. In this paper, we
propose a method to inherently enhance the robustness and inference accuracy of
BayNNs deployed in IMC architectures. To achieve this, we introduce a novel
normalization layer combined with stochastic affine transformations. Empirical
results in various benchmark datasets show a graceful degradation in inference
accuracy, with an improvement of up to
Scalable Emulation of Sign-ProblemFree Hamiltonians with Room Temperature p-bits
The growing field of quantum computing is based on the concept of a q-bit
which is a delicate superposition of 0 and 1, requiring cryogenic temperatures
for its physical realization along with challenging coherent coupling
techniques for entangling them. By contrast, a probabilistic bit or a p-bit is
a robust classical entity that fluctuates between 0 and 1, and can be
implemented at room temperature using present-day technology. Here, we show
that a probabilistic coprocessor built out of room temperature p-bits can be
used to accelerate simulations of a special class of quantum many-body systems
that are sign-problemfree or stoquastic, leveraging the well-known
Suzuki-Trotter decomposition that maps a -dimensional quantum many body
Hamiltonian to a +1-dimensional classical Hamiltonian. This mapping allows
an efficient emulation of a quantum system by classical computers and is
commonly used in software to perform Quantum Monte Carlo (QMC) algorithms. By
contrast, we show that a compact, embedded MTJ-based coprocessor can serve as a
highly efficient hardware-accelerator for such QMC algorithms providing several
orders of magnitude improvement in speed compared to optimized CPU
implementations. Using realistic device-level SPICE simulations we demonstrate
that the correct quantum correlations can be obtained using a classical
p-circuit built with existing technology and operating at room temperature. The
proposed coprocessor can serve as a tool to study stoquastic quantum many-body
systems, overcoming challenges associated with physical quantum annealers.Comment: Fixed minor typos and expanded Appendi
Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS FETs
Probabilistic computing is a novel computing scheme that offers a more
efficient approach than conventional CMOS-based logic in a variety of
applications ranging from optimization to Bayesian inference, and invertible
Boolean logic. The probabilistic-bit (or p-bit, the base unit of probabilistic
computing) is a naturally fluctuating entity that requires tunable
stochasticity; by coupling low-barrier stochastic Magnetic Tunnel Junctions
(MTJs) with a transistor circuit, a compact implementation is achieved. In this
work, through integrating stochastic MTJs with 2D-MoS FETs, the first
on-chip realization of a key p-bit building block displaying
voltage-controllable stochasticity is demonstrated. In addition, supported by
circuit simulations, this work provides a careful analysis of the three
transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how
the characteristics of each component influence the overall p-bit output. This
understanding of the interplay between the characteristics of the transistors
and the MTJ is vital for the construction of a fully functioning p-bit, making
the design rules presented in this article key for future experimental
implementations of scaled on-chip p-bit networks
MEMSORN: Self-organization of an inhomogeneous memristive hardware for sequence learning
Learning is a fundamental component for creating intelligent machines. Biological intelligence orchestrates synaptic and neuronal learning at multiple time-scales to self-organize populations of neurons for solving complex tasks. Inspired by this, we design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorporates resistive memory (RRAM) in its synapses and neurons which configure their state based on Hebbian and Homeostatic plasticity respectively. For the first time, we derive these plasticity rules directly from the statistical measurements of our fabricated RRAM-based neurons and synapses. These “technologically plausible” learning rules exploit the intrinsic variability of the devices and improve the accuracy of the network on a sequence learning task by 30%. Finally, we compare the performance of MEMSORN to a fully-randomly set-up recurrent network on the same task, showing that self-organization improves the accuracy by more than 15%. This work demonstrates the importance of the device-circuit-algorithm co-design approach for implementing brain-inspired computing hardware
Probabilistic-Bits based on Ferroelectric Field-Effect Transistors for Stochastic Computing
A probabilistic-bit (p-bit) is the fundamental building block in the circuit
network of a stochastic computing, and it could produce a continuous random
bit-stream with tunable probability. Utilizing the stochasticity in few-domain
ferroelectric material(FE), we propose for the first time, the p-bits based on
ferroelectric FET. The stochasticity of the FE p-bits stems from the thermal
noise-induced lattice vibration, which renders dipole fluctuations and is
tunable by an external electric field. The impact of several key FE parameters
on p-bits' stochasticity is evaluated, where the domain properties are revealed
to play crucial roles. Furthermore, the integer factorization based on FE
p-bits circuit network is performed to verify its functionality, and the
accuracy is found to depend on FE p-bits' stochasticity. The proposed FE p-bits
possess the advantages of both extremely low hardware coast and the
compatibility with CMOS-technology, rendering it a promising candidate for
stochastic computing applications.Comment: 23 pages, 7 figures and supplementary materials with 3 note