An FPGA Implementation of Chaos based Image Encryption and its Performance Analysis

Today, hardware chip design with FPGA implementation for designing secure crypto processor is a growing topic due to rapidly increasing attack on digital images over internet network. In this paper, an FPGA implementation of Chaotic Map based two phase image encryption technique is proposed. First phase consists of pixel position permutation and second phase consists of bit value position permutation among different bit planes. In the first phase, original pixel values remain unchanged and in second phase, though pixel values are not directly changed, but finally due to position permutation over bitplanes, values are also modified. These permutations in first and second phase are done by using chaotic behaviour of Arnold Cat Map and Logistic Map respectively. A complete analysis on robustness of the method is shown. Correlation, Encryption time, Decryption time and key sensitivity show that the proposed crypto processor offers high security and reliable encryption speed for real-time image encryption and transmission

Implementation of secure SPN chaos-based cryptosystem on FPGA

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