2 research outputs found
Efficient algorithm and architecture for implementation of multiplier circuits in modern EPGAs
High speed multiplication in Field Programmable Gate Arrays is often performed either using logic cells or with built-in DSP blocks. The latter provides the highest performance for arithmetic operations while being also optimized in terms of power and area utilization. Scalability of input operands is limited to that of a single DSP block and the current CAD tools provide little help when the designer needs to build larger arithmetic blocks. The present thesis proposes an effective approach to the problem of building large integer multipliers out of smaller ones by giving two algorithms to the system designer, for a given FPGA technology. Large word length is required in applications such as cryptography and video processing. The first proposed algorithm partitions large input multipliers into an architecture-aware design. The second algorithm then places the generated design in an optimal layout minimizing interconnect delay. The thesis concludes with simulation and hardware generated data to support the proposed algorithms
Uso eficiente de aritm茅tica redundante en FPGAs
Hasta hace pocos a帽os, la utilizaci贸n de aritm茅tica redundante en FPGAs hab铆a
sido descartada por dos razones principalmente. En primer lugar, por el buen
rendimiento que ofrec铆an los sumadores de acarreo propagado, gracias a la l贸gica de
de acarreo que pose铆an de f谩brica y al peque帽o tama帽o de los operandos en las
aplicaciones t铆picas para FPGAs. En segundo lugar, el excesivo consumo de 谩rea que
las herramientas de s铆ntesis obten铆an cuando mapeaban unidades que trabajan en carrysave.
En este trabajo, se muestra que es posible la utilizaci贸n de aritm茅tica redundante
carry-save en FPGAs de manera eficiente, consiguiendo un aumento en la velocidad de
operaci贸n con un consumo de recursos razonable. Se ha introducido un nuevo formato
redundante doble carry-save y se ha demostrado que la manera 贸ptima para la
realizaci贸n de multiplicadores de elevado ancho de palabra es la combinaci贸n de
multiplicadores empotrados con sumadores carry-save.Till a few years ago, redundant arithmetic had been discarded to be use in FPGA
mainly for two reasons. First, the efficient results obtained using carry-propagate adders
thanks to the carry-logic embedded in FPGAs and the small sizes of operands in typical
FPGA applications. Second, the high number of resources that the synthesis tools
utilizes to implement carry-save circuits.
In this work, it is demonstrated that carry-save arithmetic can be efficiently used
in FPGA, obtaining an important speed improvement with a reasonable area cost. A
new redundant format, double carry-save, has been introduced, and the optimal
implementation of large size multipliers has been shown based on embedded multipliers
and carry-save adders