2,110 research outputs found
Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage
We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET. For the purpose of this paper, we developed a multiscale simulation framework that enables the evaluation of variability in the programming window of a flash cell with sub-20-nm gate length. Furthermore, we studied the threshold voltage variability due to random dopant fluctuations and fluctuations in the distribution of the molecular clusters in the cell. The simulation framework and the general conclusions of our work are transferrable to flash cells based on alternative molecules used for a storage media
Impact of atomistic device variability on analogue circuit design
Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs.
Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm âatomisticâ devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem.
Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC
Via-configurable transistors array: a regular design technique to improve ICs yield
Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Our objective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-Ripple Adders from 4 bits to 64 bits.Peer ReviewedPostprint (published version
Electronic Transport in 2D-Based Printed FETs from a Multiscale Perspective
The authors gratefully acknowledge the ERC PEP2D (contract no. 770047) and H2020 WASP (contract no. 825213) and the Crosslab Department of Excellence project for financial support. E.G.M. also acknowledges the support by the Spanish MCI through the project PID2020-116518GB-I00 and by the Junta de Andalucia-Consejeria de Economia y Conocimiento/FEDER-EU through the Project A-TIC-646-UGR20.
Open access funding provided by Universita degli Studi di Pisa within the CRUI-CARE Agreement.As 2D materials (2DMs) gain the research limelight as a technological option
for obtaining on-demand printed low-cost integrated circuits with reduced
environmental impact, theoretical methods able to provide the necessary
fabrication guidelines acquire fundamental importance. Here, a multiscale
modeling technique is exploited to study electronic transport in devices
consisting of a printed 2DM network of flakes. The approach implements a
Monte Carlo scheme to generate the flake distribution. By means of ab initio
density functional theory calculations together with non equilibrium Greenâs
functions formalism, detailed physical insights on flake-to-flake transport
mechanisms are provided. This later feeds a 3D drift-diffusion and Poisson
solution to compute self-consistently transport and electrostatics in the
device. The method is applied to MoS2 and graphene-based dielectrically
gated FETs, highlighting the impact of the structure density and variability on
the mobility and sheet resistance. The prediction capability of the proposed
approach is validated against electrical measurements of in-house printed
graphene conductive lines as a function of film thickness, demonstrating its
strong potential as a guide for future experimental activity in the field.ERC PEP2D 770047H2020 WASP 825213Crosslab Department of Excellence projectSpanish Government PID2020-116518GB-I00Junta de Andalucia-Consejeria de Economia y Conocimiento/FEDER-EU A-TIC-646-UGR20Universita degli Studi di Pisa within the CRUI-CARE Agreemen
Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability
The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters.
A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuationsâthe dominant source of statistical variabilityâincluded in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densitiesâemulating the characteristic condition of BTI degradationâresult in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions.
The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers
Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states
A new type of deterministic (non-probabilistic) computer logic system
inspired by the stochasticity of brain signals is shown. The distinct values
are represented by independent stochastic processes: independent voltage (or
current) noises. The orthogonality of these processes provides a natural way to
construct binary or multi-valued logic circuitry with arbitrary number N of
logic values by using analog circuitry. Moreover, the logic values on a single
wire can be made a (weighted) superposition of the N distinct logic values.
Fuzzy logic is also naturally represented by a two-component superposition
within the binary case (N=2). Error propagation and accumulation are
suppressed. Other relevant advantages are reduced energy dissipation and
leakage current problems, and robustness against circuit noise and background
noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are
also nonexistent because the logic value is an AC signal. A similar logic
system can be built with orthogonal sinusoidal signals (different frequency or
orthogonal phase) however that has an extra 1/N type slowdown compared to the
noise-based logic system with increasing number of N furthermore it is less
robust against time delay effects than the noise-based counterpart.Comment: Accepted for publication by Physics Letters A, on December 23, 200
Product assurance technology for custom LSI/VLSI electronics
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification
Statistical circuit simulations - from âatomisticâ compact models to statistical standard cell characterisation
This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated
Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages
A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability.
The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling.
A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Greenâs Function (GF) approach can be seen as a breakthrough methodology.
One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits.
This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations
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