THE USAGE OF LAMBERT W FUNCTION FOR IDENTIFICATION AND SPEED CONTROL OF A DC MOTOR

The paper proposes a new method of identifying the linear model of a DC motor. The parameter estimation is based on the closed-loop step response of the DC motor under a proportional controller. For the application of the method, a deliberate delay of the measured speed was introduced. The paper considers the speed regulation of the direct current motor with negligible inductance by applying 1-DOF and 2-DOF, proportional integral retarded controllers. The proportional and integral gain of the PI retarded controllers was received by using a pole placement method on the identified model. The Lambert W function was applied for the identification and in designing the controller with the purpose of finding the rightmost poles of the closed-loop as well as the boundary conditions for selecting the gain of the PI controller. The robustness of the calculated controllers was considered under the effect of an disturbance, uncertainty in each of the DC motor parameters as well as perturbations in time delay

Introducing Asynchronicity to Probabilistic Hyperproperties

Probabilistic hyperproperties express probabilistic relations between different executions of systems with uncertain behavior. HyperPCTL allows to formalize such properties, where quantification over probabilistic schedulers resolves potential non-determinism. In this paper we propose an extension named AHyperPCTL to additionally introduce asynchronicity between the observed executions by quantifying over stutter-schedulers, which may randomly decide to delay scheduler decisions by idling. To our knowledge, this is the first asynchronous extension of a probabilistic branching-time hyperlogic. We show that AHyperPCTL can express interesting information-flow security policies, and propose a model checking algorithm for a decidable fragment.Comment: to be published in the Proceedings of QEST 202

The Ising model and Special Geometries

We show that the globally nilpotent G-operators corresponding to the factors of the linear differential operators annihilating the multifold integrals $\chi^{(n)}$ of the magnetic susceptibility of the Ising model ($n \le 6$) are homomorphic to their adjoint. This property of being self-adjoint up to operator homomorphisms, is equivalent to the fact that their symmetric square, or their exterior square, have rational solutions. The differential Galois groups are in the special orthogonal, or symplectic, groups. This self-adjoint (up to operator equivalence) property means that the factor operators we already know to be Derived from Geometry, are special globally nilpotent operators: they correspond to "Special Geometries". Beyond the small order factor operators (occurring in the linear differential operators associated with $\chi^{(5)}$ and $\chi^{(6)}$), and, in particular, those associated with modular forms, we focus on the quite large order-twelve and order-23 operators. We show that the order-twelve operator has an exterior square which annihilates a rational solution. Then, its differential Galois group is in the symplectic group $Sp(12, \mathbb{C})$. The order-23 operator is shown to factorize in an order-two operator and an order-21 operator. The symmetric square of this order-21 operator has a rational solution. Its differential Galois group is, thus, in the orthogonal group $SO(21, \mathbb{C})$.Comment: 33 page

Saber on ESP32

Saber, a CCA-secure lattice-based post-quantum key encapsulation scheme, is one of the second round candidate algorithms in the post-quantum cryptography standardization process of the US National Institute of Standards and Technology (NIST) in 2019. In this work, we provide an efficient implementation of Saber on ESP32, an embedded microcontroller designed for IoT environment with WiFi and Bluetooth support. RSA coprocessor was used to speed up the polynomial multiplications for Kyber variant in a CHES 2019 paper. We propose an improved implementation utilizing the big integer coprocessor for the polynomial multiplications in Saber, which contains significant lower software overhead and takes a better advantage of the big integer coprocessor on ESP32. By using the fast implementation of polynomial multiplications, our single-core version implementation of Saber takes 1639K, 2123K, 2193K clock cycles on ESP32 for key generation, encapsulation and decapsulation respectively. Benefiting from the dual core feature on ESP32, we speed up the implementation of Saber by rearranging the computing steps and assigning proper tasks to two cores executing in parallel. Our dual-core version implementation takes 1176K, 1625K, 1514K clock cycles for key generation, encapsulation and decapsulation respectively

A 334µW 0.158mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Extended Version

The hard mathematical problems that assure the security of our current public-key cryptography (RSA, ECC) are broken if and when a quantum computer appears rendering them ineffective for use in the quantum era. Lattice based cryptography is a novel approach to public key cryptography, of which the mathematical investigation (so far) resists attacks from quantum computers. By choosing a module learning with errors (MLWE) algorithm as the next standard, National Institute of Standard \& Technology (NIST) follows this approach. The multiplication of polynomials is the central bottleneck in the computation of lattice based cryptography. Because public key cryptography is mostly used to establish common secret keys, focus is on compact area, power and energy budget and to a lesser extent on throughput or latency. While most other work focuses on optimizing number theoretic transform (NTT) based multiplications, in this paper we highly optimize a Toom-Cook based multiplier. We demonstrate that a memory-efficient striding Toom-Cook with lazy interpolation, results in a highly compact, low power implementation, which on top enables a very regular memory access scheme. To demonstrate the efficiency, we integrate this multiplier into a Saber post-quantum accelerator, one of the four NIST finalists. Algorithmic innovation to reduce active memory, timely clock gating and shift-add multiplier has helped to achieve 38\% less power than state-of-the art PQC core, 4 $\times$ less memory, 36.8\% reduction in multiplier energy and 118$\times$ reduction in active power with respect to state-of-the-art Saber accelerator (not silicon verified). This accelerator consumes $0.158mm^2$ active area which is lowest reported till date despite process disadvantages of the state-of-the-art designs

On The Parallelization Of Integer Polynomial Multiplication

With the advent of hardware accelerator technologies, multi-core processors and GPUs, much effort for taking advantage of those architectures by designing parallel algorithms has been made. To achieve this goal, one needs to consider both algebraic complexity and parallelism, plus making efficient use of memory traffic, cache, and reducing overheads in the implementations. Polynomial multiplication is at the core of many algorithms in symbolic computation such as real root isolation which will be our main application for now. In this thesis, we first investigate the multiplication of dense univariate polynomials with integer coefficients targeting multi-core processors. Some of the proposed methods are based on well-known serial classical algorithms, whereas a novel algorithm is designed to make efficient use of the targeted hardware. Experimentation confirms our theoretical analysis. Second, we report on the first implementation of subproduct tree techniques on many-core architectures. These techniques are basically another application of polynomial multiplication, but over a prime field. This technique is used in multi-point evaluation and interpolation of polynomials with coefficients over a prime field