The Integration of Multiple and Diverse Knowledge Representation Paradigms using a Blackboard Architecture

There is increasing evidence that designers of future real-time embedded systems are turning to knowledge-based techniques in order to solve complex problems where algorithmic techniques have failed to produce a solution. In addition, many applications have been mandated to use the Ada programming language for all implementation software, including the knowledge-based components. This thesis identifies three essential requirements needed to support the construction of these systems: first, the need to provide a library of Ada knowledge-based components that supports a variety of knowledge representation paradigms to model the diverse expert domains being encountered in complex applications; second, the need to provide the user with the means of creating and controlling multiple independent instances of the knowledge-based components to cope with the complexity and scale of the implementations; and third, the need to provide an integrating architecture in which the knowledge-based components may be embedded directly into an application environment. These requirements have been satisfied by using ideas derived from the concept of abstract data types to construct a library of knowledge-based components; the components have been called abstract knowledge types. Subsequently, multiple instances of the abstract knowledge types have been integrated in modules called knowledge sources, which model specific problem knowledge domains. The knowledge sources have been used to construct a blackboard architecture. The abstract knowledge types have been used to build a prototype university timetabling system in order to demonstrate their use. The research has shown that the abstract knowledge type integration approach results in a uniform implementation strategy for both conventional and knowledge-based components

Reification: A Process to Configure Java Realtime Processors

Real-time systems require stringent requirements both on the processor and the software application. The primary concern is speed and the predictability of execution times. In all real-time applications the developer must identify and calculate the worst case execution times (WCET) of their software. In almost all cases the processor design complexity impacts the analysis when calculating the WCET. Design features which impact this analysis include cache and instruction pipelining. With both cache and pipelining the time taken for a particular instruction can vary depending on cache and pipeline contents. When calculating the WCET the developer must ignore the speed advantages from these enhancements and use the normal instruction timings. This investigation is about a Java processor targeted to run within an FPGA environment (Java soft chip) supporting Java real-time applications. The investigation focuses on a simple processor design that allows simple analysis of WCET. The processor design has no cache and no instruction pipeline enhancements yet achieves higher performance than existing designs with these enhancements. The investigation centers on a process that translates Java byte codes and folds these translated codes into a modified Harvard Micro Controller (HMC). The modifications include better alignment with the application code and take advantage of the FPGA’s parallel capability. A prototyped ontology is used where the top level categories defined by Sowa are expanded to support the process. The proposed HMC and process are used to produce investigation results. Performance testing using the Sobel edge detection algorithm is used to compare the results with the only Java processor claiming real-time abilities

Simulation verification techniques study

Results are summarized of the simulation verification techniques study which consisted of two tasks: to develop techniques for simulator hardware checkout and to develop techniques for simulation performance verification (validation). The hardware verification task involved definition of simulation hardware (hardware units and integrated simulator configurations), survey of current hardware self-test techniques, and definition of hardware and software techniques for checkout of simulator subsystems. The performance verification task included definition of simulation performance parameters (and critical performance parameters), definition of methods for establishing standards of performance (sources of reference data or validation), and definition of methods for validating performance. Both major tasks included definition of verification software and assessment of verification data base impact. An annotated bibliography of all documents generated during this study is provided

Four-Wave Mixing and Optical Phase Conjugation in Vertical Cavity Surface Emitting Devices

Four-wave mixing (FWM), a nonlinear optical process, was investigated in resonant cavity light emitting diodes (RCLEDs) and vertical cavity surface emitting lasers (VCSELs) below lasing threshold. These semiconductor photonic devices consisted of an optical gain region of quantum wells sandwiched between two distributed Bragg reflector (DBR) mirrors. Pump and probe lasers were injected into the devices to generate FWM. The dependence of FWM on bias current, pump laser power, and spectral and spatial separation between pump and probe lasers was investigated experimentally. A computer model of FWM based on the wave and carrier density equations was developed and agreed well with experimental results. Conjugate reflectivities of I were obtained in the VCSEL when bias current was below threshold but above transparency. Reasonable conjugate reflectivities were obtained for pump-probe detunings up to 2 GHz in both devices. Noncollinear FWM was performed for the first time in VCSELs or RCLEDs at angles up to 10°. Both experiment and model showed the possibility of generating a strong reflected conjugate signal while minimizing the reflected pump signal. The noncollinear FWM demonstrated the possibility of phase front conjugation for correcting aberrated signals in vertical cavity devices

The Pacifican, September 22, 1978

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