A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture

The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint(area/power) is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.Comment: 18 pages, 6 figures, International journal of VLSI design & Communication Systems (VLSICS

Experimental investigation of semiconductor losses in cryogenic DC-DC converters

As high-temperature superconductor technology approaches commercial applications, for example superconducting magnetic energy storage, superconducting fault current limiters, and superconducting rotary machines for marine propulsion, it is timely to consider the possibility of integrating the associated control equipment into the cryostat with the superconductor. This may bring benefits in terms of the performance of the power electronics or may enable other system benefits such as higher voltage lower current feedthroughs which reduce heat leakage into the cryostat. This Thesis studies the performance of several DC-DC power conversion techniques at temperatures down to 20 K. In particular hard switching, synchronous rectifier, zero-voltageswitching and multi-level circuit prototypes are examined, focusing on the losses in the semiconductor devices. The prototypes operated from 120 V and 500 V DC supplies at power levels up to 500 W using MOSFET devices and ultrafast, Schottky and silicon carbide diodes. The semiconductors were all in commercial TO220 packages. Although MOSFET on-state resistance was found to drop by a factor of approximately six at cryogenic temperatures, the device switching speed and switching losses were relatively insensitive to temperature. The diode on-state voltage increased by 20-30 % at low temperatures whilst reverse recovery and the associated losses decreased by a factor of up to ten. The total semiconductor losses in all prototypes reduced at low temperatures, typically exhibiting a minimum value in the region of 50-100 K. The performance of the hard switching and synchronous rectifier circuits was limited at cryogenic temperatures by switching losses, even though the dead time in the synchronous rectifier was adjusted to compensate for the increase in MOSFET gate threshold voltage at low temperatures. The zero-voltage-switching prototype offered the largest reduction in semiconductor losses at low temperatures, the losses were reduced to 18 % of the room temperature value. Furthermore, since the remaining losses were almost entirely due to MOSFET conduction, further reductions could be easily achieved by paralleling additional devices. The performance of the multi-level circuits was limited by switching losses and the large number of series connected devices; however, a zero-voltage-switching synchronous rectifier variant of the circuit was suggested to overcome some of these limitations.EThOS - Electronic Theses Online ServiceGBUnited Kingdo