Application of semi-definite relaxation to multiuser detection in a CDMA context

- De nombreuses problématiques de traitement du signal se ramènent à la résolution d'un problème d'optimisation combinatoire. Récemment, la Relaxation Semi-Définie (SDR) s'est révélée être une approche prometteuse en la matière, permettant une relaxation réaliste de problèmes NP-complets. Dans cet article, nous présentons un algorithme efficace pour résoudre SDR avec une complexité réduite. L'objet principale est d'étudier des méthodes de programmation non linéaires qui reposent sur un changement de variable consistant à remplacer la variable symétrique définie positive X intervenant dans SDR par une variable rectangulaire V à travers la décomposition X =V TV. Des résultats récents sur les rangs de matrices de corrélations extrémales permettent de conduire à un algorithme de faible complexité avec une perte négligeable en matière de performances. Des résultats très encourageants ont été obtenus pour résoudre des problèmes d'optimisation combinatoire de grande dimension, tel que celui qui intervient dans la détection multi utilisateur en mode CDMA

Variable-Complexity Trellis Decoding of Binary Convolutional Codes

Considers trellis decoding of convolutional codes with selectable effort, as measured by decoder complexity. Decoding is described for single parent codes with a variety of complexities, with performance near that of the optimal fixed receiver complexity coding system. Effective free distance is examined. Criteria are proposed for ranking parent codes, and some codes found to be best according to the criteria are tabulated, Several codes with effective free distance better than the best code of comparable complexity were found. Asymptotic (high SNR) performance analysis and error propagation are discussed. Simulation results are also provided

Detection for a Statistically-Known, Time-Varying Dispersive Channel

Detection for the statistically known channel (SKC) is aimed at obtaining good performance in situations where our statistical knowledge of a time-varying channel is good, and where other equalization/detection schemes are either too complex to implement, or their performance is limited due to the rapidity of channel fading, or where we are simply unable to perform channel estimation. By using a statistical characterization of the channel, we develop a new detector that performs maximum-likelihood sequence estimation (MLSE) (given the channel model) on blocks of N symbols. Both symbol-spaced and fractionally spaced samples are used, to obtain two different detectors, that are generalizations of those devised for optimal block schemes on nondispersive channels. The detector that uses fractionally spaced samples is shown to outperform the detector that uses symbol-spaced samples. The performance of both appears to approach that of the corresponding known channel (KC) detector as the block length increases. We also numerically evaluate the SKC detector performance under conditions where the channel parameters (statistics) are incorrectly estimated, and show that the fractionally spaced detector is fairly robust to modeling errors. Finally, we devise a sliding block algorithm, for use when transmitting more than N symbols

New VLSI design of a MAP/BCJR decoder.

Any communication channel suffers from different kinds of noises. By employing forward error correction (FEC) techniques, the reliability of the communication channel can be increased. One of the emerging FEC methods is turbo coding (iterative coding), which employs soft input soft output (SISO) decoding algorithms like maximum a posteriori (MAP) algorithm in its constituent decoders. In this thesis we introduce a design with lower complexity and less than 0.1dB performance loss compare to the best performance observed in Max-Log-MAP algorithm. A parallel and pipeline design of a MAP decoder suitable for ASIC (Application Specific Integrated Circuits) is used to increase the throughput of the chip. The branch metric calculation unit is studied in detail and a new design with lower complexity is proposed. The design is also flexible to communication block sizes, which makes it ideal for variable frame length communication systems. A new even-spaced quantization technique for the proposed MAP decoder is utilized. Normalization techniques are studied and a suitable technique for the Max-Log-MAP decoder is explained. The decoder chip is synthesized and implemented in a 0.18 mum six-layer metal CMOS technology. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .S23. Source: Masters Abstracts International, Volume: 43-05, page: 1783. Adviser: Majid Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Robust digital image watermarking algorithms for copyright protection

Digital watermarking has been proposed as a solution to the problem of resolving copyright ownership of multimedia data (image, audio, video). The work presented in this thesis is concerned with the design of robust digital image watermarking algorithms for copyright protection. Firstly, an overview of the watermarking system, applications of watermarks as well as the survey of current watermarking algorithms and attacks, are given. Further, the implementation of feature point detectors in the field of watermarking is introduced. A new class of scale invariant feature point detectors is investigated and it is showed that they have excellent performances required for watermarking. The robustness of the watermark on geometrical distortions is very important issue in watermarking. In order to detect the parameters of undergone affine transformation, we propose an image registration technique which is based on use of the scale invariant feature point detector. Another proposed technique for watermark synchronization is also based on use of scale invariant feature point detector. This technique does not use the original image to determine the parameters of affine transformation which include rotation and scaling. It is experimentally confirmed that this technique gives excellent results under tested geometrical distortions. In the thesis, two different watermarking algorithms are proposed in the wavelet domain. The first algorithm belongs to the class of additive watermarking algorithms which requires the presence of original image for watermark detection. Using this algorithm the influence of different error correction codes on the watermark robustness is investigated. The second algorithm does not require the original image for watermark detection. The robustness of this algorithm is tested on various filtering and compression attacks. This algorithm is successfully combined with the aforementioned synchronization technique in order to achieve the robustness on geometrical attacks. The last watermarking algorithm presented in the thesis is developed in complex wavelet domain. The complex wavelet transform is described and its advantages over the conventional discrete wavelet transform are highlighted. The robustness of the proposed algorithm was tested on different class of attacks. Finally, in the thesis the conclusion is given and the main future research directions are suggested

Realizing Software Defined Radio - A Study in Designing Mobile Supercomputers.

The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or Software Defined Radio (SDR), has a number of advantages. These include support for multiple protocols, faster time-to-market, higher chip volumes, and support for late implementation changes. The challenge is to achieve this under the power budget of a mobile device. Wireless communications belong to an emerging class of applications with the processing requirements of a supercomputer but the power constraints of a mobile device -- mobile supercomputing. This thesis presents a set of design proposals for building a programmable wireless communication solution. In order to design a solution that can meet the lofty requirements of SDR, this thesis takes an application-centric design approach -- evaluate and optimize all aspects of the design based on the characteristics of wireless communication protocols. This includes a DSP processor architecture optimized for wireless baseband processing, wireless algorithm optimizations, and language and compilation tool support for the algorithm software and the processor hardware. This thesis first analyzes the software characteristics of SDR. Based on the analysis, this thesis proposes the Signal-Processing On-Demand Architecture (SODA), a fully programmable multi-core architecture that can support the computation requirements of third generation wireless protocols, while operating within the power budget of a mobile device. This thesis then presents wireless algorithm implementations and optimizations for the SODA processor architecture. A signal processing language extension (SPEX) is proposed to help the software development efforts of wireless communication protocols on SODA-like multi-core architecture. And finally, the SPIR compiler is proposed to automatically map SPEX code onto the multi-core processor hardware.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/61760/1/linyz_1.pd