The Construction of Verification Models for Embedded Systems

The usefulness of verification hinges on the quality of the verification model. Verification is useful if it increases our confidence that an artefact bahaves as expected. As modelling inherently contains non-formal elements, the qualityof models cannot be captured by purely formal means. Still, we argue that modelling is not an act of irrationalism and unpredictable geniality, but follows rational arguments, that often remain implicit. In this paper we try to identify the tacit rationalism in the model construction as performed by most people doing modelling for verification. By explicating the different phases, arguments, and design decisions in the model construction, we try to develop guidelines that help to improve the process of model construction and the quality of models

A Study to Optimize Heterogeneous Resources for Open IoT

Recently, IoT technologies have been progressed, and many sensors and actuators are connected to networks. Previously, IoT services were developed by vertical integration style. But now Open IoT concept has attracted attentions which achieves various IoT services by integrating horizontal separated devices and services. For Open IoT era, we have proposed the Tacit Computing technology to discover the devices with necessary data for users on demand and use them dynamically. We also implemented elemental technologies of Tacit Computing. In this paper, we propose three layers optimizations to reduce operation cost and improve performance of Tacit computing service, in order to make as a continuous service of discovered devices by Tacit Computing. In optimization process, appropriate function allocation or offloading specific functions are calculated on device, network and cloud layer before full-scale operation.Comment: 3 pages, 1 figure, 2017 Fifth International Symposium on Computing and Networking (CANDAR2017), Nov. 201

QYPS HPS Interconnect verification methodology for SOC FPGA

FPGA yang mengandungi unit pemprosesan terbenam adalah aliran masa depan bagi aplikasi-aplikasi berprestasi tinggi dan berkuasa rendah. Saling-sambung HPS Qsys, telah direka untuk menyambungkan FPGA dengan sistem pemprosesan terbenam (HPS) melalui satu klik tetikus. Walaupun, model berfungsi bas (BFM) sering digunakan bagi metodologi pengesahan untuk saling-sambung Qsys, HPS melibatkan protocol-protokol antaramuka yang berbeza. Tugas untuk merekabentuk dan mengesahkan BFM akan mengambil masa yang panjang. Oleh itu, metodologi pengesahan yang baru telah dicadangkan untuk saling-sambung HPS Qsys di dalam projek penyelidikan ini. Bagi kaedah pengesahan yang dicadangkan, saling-sambung HPS Qsys akan digabungkan ke dalam bangku ujian pengesahan HPS RTL melalui sejenis rekabentuk suis pin. Selain itu, rekabentuk Qsys juga digabungkan ke dalam simulasi ujian HPS RTL. Lima antaramuka Qsys, iaitu UART, SPI, FPGA-CTI, FPGA interrupt dan boot-from-FPGA telah berjaya disahkan melalui metodologi pengesahan yang dicadangkan. Berbanding dengan ujian pengesahan HPS RTL, masa simulasi yang lebih pendek telah diperhatikan semasa menguji fungsi yang sama dalam cadangan kaedah pengesahan. Field programmable gate array (FPGA) with embedded processor is the future trend for the high performance and low power applications. Qsys HPS interconnect is designed to provide seamless connection between FPGA and the embedded hard processor system (HPS) through a click of mouse. Although bus functional model (BFM) is extensively used in existing Qsys non-HPS interconnect verification methodology, HPS consists of many different interface protocols. The task of develop and validate the BFMs become the bottleneck in verification. A new Qsys HPS interconnect verification methodology has been proposed in this research project. In the proposed verification methodology, the Qsys HPS interconnect will be integrated into HPS RTL verification test bench through a pin switch architecture. Besides, the Qsys design is also integrated into HPS RTL simulation test flow. Five different Qsys interface designs, namely UART, SPI, FPGA-CTI, FPGA interrupt and boot-from-FPGA have been successfully verified using the proposed verification methodology. Shorter simulation time has been observed while testing same function in the proposed verification methodology as compared to HPS RTL verification test

Block the Root Takeover: Validating Devices Using Blockchain Protocol

This study addresses a vulnerability in the trust-based STP protocol that allows malicious users to target an Ethernet LAN with an STP Root-Takeover Attack. This subject is relevant because an STP Root-Takeover attack is a gateway to unauthorized control over the entire network stack of a personal or enterprise network. This study aims to address this problem with a potentially trustless research solution called the STP DApp. The STP DApp is the combination of a kernel /net modification called stpverify and a Hyperledger Fabric blockchain framework in a NodeJS runtime environment in userland. The STP DApp works as an Intrusion Detection System (IPS) by intercepting Ethernet traffic and blocking forged Ethernet frames sent by STP Root-Takeover attackers. This study’s research methodology is a quantitative pre-experimental design that provides conclusive results through empirical data and analysis using experimental control groups. In this study, data collection was based on active RAM utilization and CPU Usage during a performance evaluation of the STP DApp. It blocks an STP Root-Takeover Attack launched by the Yersinia attack tool installed on a virtual machine with the Kali operating system. The research solution is a test blockchain framework using Hyperledger Fabric. It is made up of an experimental test network made up of nodes on a host virtual machine and is used to validate Ethernet frames extracted from stpverify