Novel high frequency electrical characterization technique for magnetic passive devices

Integrated magnetic components are key elements of the Power Supply on Chip modules. Due to the application requirements, these magnetic devices work at very high frequency and have low inductances. Conventional small-signal tests do not provide all the required information about the magnetic device. Hence, it is important to develop new set-ups to apply large signals to accurately measure the performance of devices under realistic operating conditions, including non-linear core effects. The proposed experimental set-up is suitable to measure the device impedance under different large-signal test conditions, similar to those in the actual converter, since the excitation current can be configured through every winding: ac current up to 0.5 A at frequencies up to 120 MHz and dc bias current up to 2 A through one or both windings. Voltage and current are measured using commercial instrumentation. Due to the characteristics of the probes and the high frequency of the test, the attenuation and delay due to the probes and the experimental set-up have to be taken into account when processing the voltage and current waveforms to calculate the impedances. The compensation test to calculate this attenuation and delay is described. Finally, the proposed set-up is validated by measuring a two-phase coupled inductors micro-fabricated on silicon

Hybrid CMOS/GaN 40-MHz Maximum 20-V Input DC–DC Multiphase Buck Converter

This paper presents a 40-MHz hybrid CMOS/GaN integrated multiphase DC-DC switched-inductor buck converter with a maximum 20-V input voltage. The half-bridge switches are realized using lateral AlGaN/GaN HEMTs, while the drivers and other circuitry are implemented in standard 180-nm CMOS. The interface between the CMOS and GaN dice is achieved through face-to-face bonding, reducing inductive parasitics for the connection to less than 15 pH. A capacitively coupled level shifter provides the gate drive for the high-side GaN switch using 5-V CMOS devices. The converter demonstrates 76% efficiency for 8:1 V conversion and over 60% efficiency for conversion ratios up to 16:1.United States. Advanced Research Projects Agency-Energy (Contract DE-AR0000452

Small Form Factor Hybrid CMOS/GaN Buck Converters for 10W Point of Load Applications

abstract: Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing. This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor. Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Investigation of Gallium Nitride Based on Power Semiconductor Devices in Polarization Super Junction Technology

Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the next generation of power devices. GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high voltage operation, GaN�based Polarization Super-Junction (PSJ) architectures demonstrate great potential. The aim of this thesis is devoted to the development of PSJ technology. Detailed analysis of the on-state behaviour of the fabricated Ohmic Gate (OG) and Schottky Gate (SG) PSJ HFETs is presented. Theoretical models for calculating the sheet densities of 2DEG and 2DHG are proposed and calibrated with numerical simulations and experimental results. To calculate the R (on, sp) of PSJ HFETs, two different gate structures (Ohmic gate and Schottky gate) are considered herein. The scaling tendency of power devices enables the emergence of multi-channel PSJ concepts. Therefore, lateral and vertical multi-channel PSJ devices based on practical implementation are also investigated. Presented calculated and simulated results show that both lateral and vertical multi-channel PSJ technologies can be well suited to break the unipolar one-dimensional material limits of GaN by orders of magnitude and achieve an excellent trade-off between R (on, sp) and voltage blocking capability provided composition and thickness control can be realised. A novel multi-polarization channel is applied to realize normally-off and high�performance vertical GaN device devices for low voltage applications based on the multi-channel PSJ and vertical MOSFET concepts. This structure is made with 2DHG introduced to realize the enhancement mode channel instead of p-GaN as in conventional vertical GaN MOSFETs. As the 2DHG depends upon growth conditions, p-type doping activation issues can be overcome. The Mg-doped layer is only used to reduce the short-channel effects, as the 2DHG layer is too thin. Two more 2DEG layers P a g e | iv are formed through AlGaN/GaN/AlGaN/GaN polarization structure, which minimizes the on-state resistance. The calculation results show this novel vertical GaN MOSFET – termed SV GaN FET - has the potential to break the GaN material limit in the trade-off between R (on, sp) and breakdown voltage at low voltages. The comprehensive set of development based on the PSJ concept gives a comprehensive overview of next-generation power electronics