Estimators for Logic Minimization and Implementation Selection of Finite State machines

This paper considers two estimation problems which occur during the implementation design for a finite state machine (FSM). The first is a precise estimation of the reduction of a programmed logic array implementation (PLA) for a FSM by logic minimization. The second concerns selection of implementation alternatives based on such estimations. Estimations give the designer a quick overview of the impact of an optimization method for FSM implementation without running the actual time-consuming algorithms. The method uses curve-fitting on results found in literature for logic minimization preceded by state-assignment. Our estimations correlate by 0.97 to those results. State-graph statistics can also be used for selection of the most profitable optimization from a set of alternatives. We tested selection between a counter based implementation, partial state coding, state-assignment and topological partitioning. The goal is selection of the alternative which has the highest probability to deliver the largest minimization of the FSM. This selection method is also empirically verified by comparing its results with results obtained by running specific optimization algorithms on machines of the MCNC benchmark set

Mascot: Microarchitecture Synthesis of Control Paths

This paper presents MASCOT (MicroArchitecture Synthesis of ConTrol paths). This synthesis system constructs the optimal microarchitecture for a control path of an instruction set processor. Input to the system is the behavioural specification of a control path. This specification is in finite state machine form which is mapped initially onto a single programmed logic array (PLA) microarchitecture. The synthesis strategy then applies a sequence of decompositions on this initial microarchitecture. This strategy follows a decision scheme until all design objectives are met. It transforms the initial microarchitecture into a complex microarchitecture of several PLAs and ROMs. Where it is impossible to meet the design objectives, the system constructs a microarchitecture which comes as close as possible to given design objectives. Design objectives are allowed on floorplan dimensions and delay. Our strategy integrates a number of known optimization methods for specific microarchitectures. Therefore this synthesis method explores a larger part of the design space than do other control path synthesis methods. Other methods are mostly bound to one microarchitecture which they optimize. Our system is not only very flexible in microarchitecture construction but also open for extension by other optimizations