4 research outputs found
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A 90.5dB DR 1MHz BW Hybrid Two Step ADC with CT Incremental and SAR ADCs
The sensors in real time data processing IoT devices require high resolution and sub-MHz data converters, usually implemented as Incremental ADCs due to the advantages of oversampling technique and low latency. In discrete time incremental (IDT) ADCs, the sampling switch non-linearity, charge injection degrade the resolution, and power hungry OPAMPs are demanded to provide fast and accurate settling for the switch-capacitor circuits. While the continuous time incremental (ICT) ADCs overcome these issues by removing the sampling switches and it also relax the OPAMPs settling accuracy to save power. A hybrid architecture of ICT ADC and SAR two step ADC is proposed to achieve high resolution at low oversampling ratio (OSR). The first ICT ADCs enable higher resolution, faster conversion speed with lower power consumption. The residual error of the ICT ADC is extracted at the last integrator output and transfers to the 2nd SAR for further conversion. In this architecture, only the mismatch between the cascade of integrators (CoIs) and decimation filter transfer functions causes 1st stage quantization noise leakage which can be solved by increasing opamp parameters instead of increasing the digital decimation filter complexity. In addition, the overall SQNR is independent of the first ICT ADC’s NTF, which gives more freedom to trade-off between the loop stability and DAC errors. A 4bits DRZ DAC with data weighted averaging (DWA) technique is adopted to reduce the clock jitter of DAC, mitigate ISI error and static mismatch errors. Based on this architecture, a 16b resolution, 1MHz signal bandwidth hybrid two step ADC is designed and measurement results are demonstrated. Important sub circuits are introduced and analyzed in detail to get the target resolution. The ADC is fabricated in AKM 180nm CMOS process with 1.8V supply voltage, it achieves a DR of 90.5dB, and SNR/SFDR/SNDR of 82.5dB/85dB/80.5dB over 1MHz BW sampled at 64MHz
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Power Efficient Architectures for High Accuracy Analog-to-Digital Converters
Incremental ADCs (IADCs) have found wide applications in sensor interface circuitry since, compared to ∆Σ ADCs, they provide low-latency high-accuracy conversion and easy multiplexing among multiple channels. On the other hand, continuous-time ∆Σ ADCs (CTDSM) have been receiving more and more attention as a power-efficient solution in targeting medium to high accuracy over wider range of signal bandwidth (tens of MHz). In this dissertation, novel configurations have been explored in both architectures for power-efficient and high-accuracy data conversion.
First, a multi-step incremental ADC (IADC) using multi-slope extended counting technique is described. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured as multi-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits as good efficiency as its second-order ∆Σ ADC counterpart. For the same accuracy, the conversion cycle is shortened by a factor of more than 2⁹ compared to the IADC1. Fabricated in 0.18-μm CMOS process, the prototype ADC occupies 0.5 mm². With a 642 kHz clock, it achieves SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step, and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 µW from a 1.5 V power supply. This gives an excellent Schreier FoM of 174.6 dB.
Secondly, a multi-step incremental ADC with extended binary counting is proposed. It achieves high accuracy by splitting one conversion cycle into two serial steps. During the first step, the ADC works as a first-order incremental ADC (IADC1). The second step reuses the single integrator and extends the accuracy to 16 bits by a two-capacitor SAR-assisted binary counting technique. For the same accuracy, the conversion cycle is shortened by a factor of more than 2⁸ as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the SAR-assisted IADC achieves a peak SNR/SNDR/DR of 97.1/96.6/100.2 dB over a 1.2 kHz bandwidth, while dissipating 33.2 μW from a 1.5 V supply. This gives a Schreier FoM of 175.8 dB and Walden FoM of 0.25 pJ/conv.-step.
Finally, the design of a continuous-time ∆Σ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging is described. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm² and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit was achieved.Keywords: Incremental ADC, multi-step operation, instrumentation and measurement, sensor interface, analog-to-digital converter, extended counting, chopper stabilization, delta-sigma ADC, multi-slope ADCsKeywords: Incremental ADC, multi-step operation, instrumentation and measurement, sensor interface, analog-to-digital converter, extended counting, chopper stabilization, delta-sigma ADC, multi-slope ADC
A Novel Power-Efficient Wireless Multi-channel Recording System for the Telemonitoring of Electroencephalography (EEG)
This research introduces the development of a novel EEG recording system that is modular, batteryless, and wireless (untethered) with the supporting theoretical foundation in wireless communications and related design elements and circuitry. Its modular construct overcomes the EEG scaling problem and makes it easier for reconfiguring the hardware design in terms of the number and placement of electrodes and type of standard EEG system contemplated for use. In this development, portability, lightweight, and applicability to other clinical applications that rely on EEG data are sought. Due to printer tolerance, the 3D printed cap consists of 61 electrode placements. This recording capacity can however extend from 21 (as in the international 10-20 systems) up to 61 EEG channels at sample rates ranging from 250 to 1000 Hz and the transfer of the raw EEG signal using a standard allocated frequency as a data carrier. The main objectives of this dissertation are to (1) eliminate the need for heavy mounted batteries, (2) overcome the requirement for bulky power systems, and (3) avoid the use of data cables to untether the EEG system from the subject for a more practical and less restrictive setting.
Unpredictability and temporal variations of the EEG input make developing a battery-free and cable-free EEG reading device challenging. Professional high-quality and high-resolution analog front ends are required to capture non-stationary EEG signals at microvolt levels. The primary components of the proposed setup are the wireless power transmission unit, which consists of a power amplifier, highly efficient resonant-inductive link, rectification, regulation, and power management units, as well as the analog front end, which consists of an analog to digital converter, pre-amplification unit, filtering unit, host microprocessor, and the wireless communication unit. These must all be compatible with the rest of the system and must use the least amount of power possible while minimizing the presence of noise and the attenuation of the recorded signal
A highly efficient resonant-inductive coupling link is developed to decrease power transmission dissipation. Magnetized materials were utilized to steer electromagnetic flux and decrease route and medium loss while transmitting the required energy with low dissipation. Signal pre-amplification is handled by the front-end active electrodes. Standard bio-amplifier design approaches are combined to accomplish this purpose, and a thorough investigation of the optimum ADC, microcontroller, and transceiver units has been carried out. We can minimize overall system weight and power consumption by employing battery-less and cable-free EEG readout system designs, consequently giving patients more comfort and freedom of movement. Similarly, the solutions are designed to match the performance of medical-grade equipment. The captured electrical impulses using the proposed setup can be stored for various uses, including classification, prediction, 3D source localization, and for monitoring and diagnosing different brain disorders.
All the proposed designs and supporting mathematical derivations were validated through empirical and software-simulated experiments. Many of the proposed designs, including the 3D head cap, the wireless power transmission unit, and the pre-amplification unit, are already fabricated, and the schematic circuits and simulation results were based on Spice, Altium, and high-frequency structure simulator (HFSS) software. The fully integrated head cap to be fabricated would require embedding the active electrodes into the 3D headset and applying current technological advances to miniaturize some of the design elements developed in this dissertation