Implementing a lightweight Schmidt-Samoa cryptosystem (SSC) for sensory communications

One of the remarkable issues that face wireless sensor networks (WSNs) nowadays is security. WSNs should provide a way to transfer data securely particularly when employed for mission-critical purposes. In this paper, we propose an enhanced architecture and implementation for 128-bit Schmidt-Samoa cryptosystem (SSC) to secure the data communication for wireless sensor networks (WSN) against external attacks. The proposed SSC cryptosystem has been efficiently implemented and verified using FPGA modules by exploiting the maximum allowable parallelism of the SSC internal operations. To verify the proposed SSC implementation, we have synthesized our VHDL coding using Quartus II CAD tool targeting the Altera Cyclone IV FPGA EP4CGX22CF19C7 device. Hence, the synthesizer results reveal that the proposed cryptographic FPGA processor recorded an attractive result in terms of critical path delay, hardware utilization, maximum operational frequency FPGA thermal power dissipation for low-power applications such as the wireless sensor networks

Trusted Computing using Enhanced Manycore Architectures with Cryptoprocessors

International audienceManycore architectures correspond to a main evolution of computing systems due to their high processing power. Many applications can be executed in parallel which provides users with a very efficient technology. Cloud computing is one of the many domains where manycore architectures will play a major role. Thus, building secure manycore architectures is a critical issue. However a trusted platform based on manycore architectures is not available yet. In this paper we discuss the main challenges and some possible solutions to enhance manycore architectures with cryptoprocessor

Design and analysis of efficient and secure elliptic curve cryptoprocessors

Elliptic Curve Cryptosystems have attracted many researchers and have been included in many standards such as IEEE, ANSI, NIST, SEC and WTLS. The ability to use smaller keys and computationally more efficient algorithms compared with earlier public key cryptosystems such as RSA and ElGamal are two main reasons why elliptic curve cryptosystems are becoming more popular. They are considered to be particularly suitable for implementation on smart cards or mobile devices. Power Analysis Attacks on such devices are considered serious threat due to the physical characteristics of these devices and their use in potentially hostile environments. This dissertation investigates elliptic curve cryptoprocessor architectures for curves defined over GF(2m) fields. In this dissertation, new architectures that are suitable for efficient computation of scalar multiplications with resistance against power analysis attacks are proposed and their performance evaluated. This is achieved by exploiting parallelism and randomized processing techniques. Parallelism and randomization are controlled at different levels to provide more efficiency and security. Furthermore, the proposed architectures are flexible enough to allow designers tailor performance and hardware requirements according to their performance and cost objectives. The proposed architectures have been modeled using VHDL and implemented on FPGA platform

Reconfigurable Architecture for Elliptic Curve Cryptography Using FPGA

The high performance of an elliptic curve (EC) crypto system depends efficiently on the arithmetic in the underlying finite field. We have to propose and compare three levels of Galois Field , , and . The proposed architecture is based on Lopez-Dahab elliptic curve point multiplication algorithm, which uses Gaussian normal basis for field arithmetic. The proposed is based on an efficient Montgomery add and double algorithm, also the Karatsuba-Ofman multiplier and Itoh-Tsujii algorithm are used as the inverse component. The hardware design is based on optimized finite state machine (FSM), with a single cycle 193 bits multiplier, field adder, and field squarer. The another proposed architecture is based on applications for which compactness is more important than speed. The FPGA’s dedicated multipliers and carry-chain logic are used to obtain the small data path. The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication, increases frequency and the speed of operation such as key generation, encryption, and decryption. Finally, we have to implement our design using Xilinx XC4VLX200 FPGA device

Cryptanalysis of CIKS-128 and CIKS-128H Suitable for Intelligent Multimedia and Ubiquitous Computing Systems

Recently, data-dependent permutations (DDP) that are very suitable for intelligent multimedia and ubiquitous computing systems have been introduced as a new cryptographic primitive for the design of fast encryption systems. The CIKS-128 and CIKS-128H block ciphers are the typical examples of DDP-based encryption algorithms. In this paper, we show that CIKS-128 and CIKS-128H are vulnerable to related-key differential attacks. We first describe how to construct their full-round related-key differential characteristics with high probabilities and then we exploit them to break the full-round CIKS-128 and CIKS-128H with 2^44, and 2^48 data/time complexities, respectively

A Holistic Systems Security Approach Featuring Thin Secure Elements for Resilient IoT Deployments

© 2020 by the authors. This is an open access article distributed under the Creative Commons Attribution License (https://creativecommons.org/licenses/by/4.0/) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.IoT systems differ from traditional Internet systems in that they are different in scale, footprint, power requirements, cost and security concerns that are often overlooked. IoT systems inherently present different fail-safe capabilities than traditional computing environments while their threat landscapes constantly evolve. Further, IoT devices have limited collective security measures in place. Therefore, there is a need for different approaches in threat assessments to incorporate the interdependencies between different IoT devices. In this paper, we run through the design cycle to provide a security-focused approach to the design of IoT systems using a use case, namely, an intelligent solar-panel project called Daedalus. We utilise STRIDE/DREAD approaches to identify vulnerabilities using a thin secure element that is an embedded, tamper proof microprocessor chip that allows the storage and processing of sensitive data. It benefits from low power demand and small footprint as a crypto processor as well as is compatible with IoT 29 requirements. Subsequently, a key agreement based on an asymmetric cryptographic scheme, namely B-SPEKE was used to validate and authenticate the source. We find that end-to-end and independent stand-alone procedures used for validation and encryption of the source data originating from the solar panel are cost-effective in that the validation is carried out once and not several times in the chain as is often the case. The threat model proved useful not so much as a panacea for all threats but provided the framework for the consideration of known threats, and therefore appropriate mitigation plans to be deployed.Peer reviewe