691 research outputs found
ATPG for Dynamic Burn-In Test in Full-Scan Circuits
Yield and reliability are two key factors affecting costs and profits in the semiconductor industry. Stress testing is a technique based on the application of higher than usual levels of stress to speed up the deterioration of electronic devices and increase yield and reliability. One of the standard industrial approaches for stress testing is high temperature burn-in. This work proposes a full-scan circuit ATPG for dynamic burn-in. The goal of the proposed ATPG approach is to generate test patterns able to force transitions into each node of a full scan circuit to guarantee a uniform distribution of the stress during the dynamic burn-in tes
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Improving timing verification and delay testing methodologies for IC designs
textThe task of ensuring the correct temporal behavior of IC designs,
both before and after fabrication, is extremely important. It is becoming
even more imperative as the demand for performance increases and process
technology advances into the deep sub-micron region.
This dissertation tackles the key issues in the timing verification
and delay testing methodologies. An efficient methodology is presented to
identify false timing paths in the timing verification methodology which utilizes
ATPG technique and timing information from an ordered list of timing
paths according to the delay information. This dissertation also presents a
speed binning methodology which utilizes structural delay tests successfully
instead of functional tests. In addition, it establishes a methodology which
quantifies the correlation between the timing verification prediction and
actual silicon measurement of timing paths. This quantification methodology
lays the foundation for further research to study the impact of deep
submicron effects on design performanceElectrical and Computer Engineerin
Scan Test Coverage Improvement Via Automatic Test Pattern Generation (Atpg) Tool Configuration
The scan test coverage improvement by using automatic test pattern generation (ATPG) tool configuration was investigated. Improving the test coverage is essential in detecting manufacturing defects in semiconductor industry so that high quality products can be supplied to consumers. The ATPG tool used was Mentor Graphics Tessent TestKompress (version 2014.1). The study was done by setting up a few experiments of utilizing and modifying ATPG commands and switches, observing the test coverage improvement from the statistical reports provided during pattern generation process and providing relatable discussions. By modifying the ATPG commands, it can be expected to have some improvement in the test coverage. The scan test patterns generated were stuck-at test patterns. Based on the experiments done, comparison was made on the different coverage readings and the most optimized method and flow of ATPG were determined. The most optimized flow gave an improvement of 0.91% in test coverage which is acceptable since this method does not involve a change in design. The test patterns generated were converted and tested using automatic test equipment (ATE) to observe its performance on real silicon. The test coverage improvement using ATPG tool instead of the design-based method is important as a faster workaround for back-end engineers to provide high quality test contents in such a short product development duration
Logic Locking based Trojans: A Friend Turns Foe
Logic locking and hardware Trojans are two fields in hardware security that
have been mostly developed independently from each other. In this paper, we
identify the relationship between these two fields. We find that a common
structure that exists in many logic locking techniques has desirable properties
of hardware Trojans (HWT). We then construct a novel type of HWT, called
Trojans based on Logic Locking (TroLL), in a way that can evade
state-of-the-art ATPG-based HWT detection techniques. In an effort to detect
TroLL, we propose customization of existing state-of-the-art ATPG-based HWT
detection approaches as well as adapting the SAT-based attacks on logic locking
to HWT detection. In our experiments, we use random sampling as reference. It
is shown that the customized ATPG-based approaches are the best performing but
only offer limited improvement over random sampling. Moreover, their efficacy
also diminishes as TroLL's triggers become longer, i.e., have more bits
specified). We thereby highlight the need to find a scalable HWT detection
approach for TroLL.Comment: 9 pages, double column, 8 figures, IEEE forma
A Total Self Checking Comparator Implementable on FPGAS Using Bist Technology
an integrated circuits (IC) "manufacturing tests" may be made easier to administer with the use of design for testability (DFT). Integrated circuits' embedded memory tests make use of the TSC (TSC) approach. We have shown the TSC method and several algorithms used in TSC for the purpose of testing embedded memory in this article. An address generator, controller, comparator, and memory are the four main components of this kind of memory TSC technology. This paper details the three memory TSC controller implementation techniques. The memory TSC controller is modelled in Verilog HDL, and its accuracy is checked using the RTL compiler before synthesis.
Here we provide a way to build TSC comparators for TSC systems that may be implemented on FPGAs—totally self-checking (TSC) systems—that can be used online. By directly measuring the output of each lookup table (LUT), this approach may be utilised to do comprehensive online diagnostics of all LUTs. This entails mapping the basic components of the comparator with a limited number of test patterns. With our technique, we can achieve exhaustive diagnosis with a small number of test patterns on the order of n [O(n)] (where n is the input number to the comparator) while yet covering all bases 100% of the time, even if we are just aware of the LUT's specs and not its exact structure. For systems that need absolute reliability, FPGAs will be a perfect fit. Our experiment also included a single-event upset (SEU) induced by neutron radiation to validate the soft error rate (SER) in a field-programmable gate array (FPGA) based on static random-access memory (SRAM)
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