Smart Power Devices and ICs Using GaAs and Wide and Extreme Bandgap Semiconductors

We evaluate and compare the performance and potential of GaAs and of wide and extreme bandgap semiconductors (SiC, GaN, Ga2O3, diamond), relative to silicon, for power electronics applications. We examine their device structures and associated materials/process technologies and selectively review the recent experimental demonstrations of high voltage power devices and IC structures of these semiconductors. We discuss the technical obstacles that still need to be addressed and overcome before large-scale commercialization commences

Viable 3C-SiC-on-Si MOSFET design disrupting current Material Technology Limitations

The cubic polytype (3C-) of Silicon Carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the Wide Band Gap (WBG) characteristics make it an excellent choice for power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Nonetheless, material related limitations originate from the advantageous fact that 3C-SiC can be grown on Silicon (Si) wafers. One of these major limitations is an almost negligible activation of the p-type dopants after ion implantation because the annealing has to take place at relatively low temperatures. In this paper, a novel process flow for a vertical 3C-SiC-on-Si MOSFET is presented to overcome the difficulties that currently exist in obtaining a p-body region through implantation. The proposed design has been accurately simulated with Technology Computer Aided Design (TCAD) process and device software and a comparison is performed with the conventional SiC MOSFET design. The simulated output characteristics demonstrated a reduced on-resistance and at the same time it is shown that the blocking capability can be maintained to the same level. The promising performance of the novel design discussed in this paper is potentially the solution needed and a huge step towards the realisation of 3C-SiC-on-Si MOSFETs with commercially grated characteristics

Effect of Boron Incorporation on Slow Interface Traps in SiO2/4H-SiC Structures

The reason for the effective removal of interface traps in SiO2/4H-SiC (0001) structures by boron (B) incorporation was investigated by employing low-temperature electrical measurements. Low-temperature capacitance–voltage and thermal dielectric relaxation current measurements revealed that the density of electrons captured in slow interface traps in B-incorporated oxide is lower than that in dry and NO-annealed oxides. These results suggest that near-interface traps can be removed by B incorporation, which is considered to be an important reason for the increase in the field-effect mobility of 4H-SiC metal–oxide–semiconductor devices. A model for the passivation mechanism is proposed that takes account of stress relaxation during thermal oxidation

Diamond power devices: State of the art, modelling and figures of merit

With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22W/cmbold dotK at room temperature) of any material, high hole mobility (> 2000cm2/Vbold dots), high critical electric field (>10MV/cm), and large bandgap (5.47eV), diamond has overwhelming advantages over silicon and other wide bandgap semiconductors (WBG) for ultra-high- voltage and high temperature applications (>3kV and >450 K, respectively). However, despite their tremendous potential, fabricated devices based on this material have not delivered yet the expected high-performance. The main reason behind this is the absence of shallow donor and acceptor species. The second reason is the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development. The third reason is that the best performances of diamond devices are expected only when the highest electric field in reverse bias can be achieved, something that has not been widely obtained yet. In this context, high temperature operation and unique device structures based on the 2DHG formation represent two alternatives which could alleviate the issue of the incomplete ionization of dopant species. Nevertheless, ultra-high temperature operations and device parallelization could result in severe thermal management issues and affect the overall stability and long-term reliability. Additionally, problems connected to the reproducibility and the long-term stability of 2DHG based-devices still need to be resolved. This review paper aims at addressing these issues by providing the power device research community with a detailed set of physical models, device designs and challenges associated to all the aspects of the diamond power device value chain, from the definition of figures of merits, the material growth and processing conditions, to packaging solutions and targeted applications. Finally, the paper will conclude with suggestions on how to design power converters with diamond devices and will provide the roadmap of diamond devices development for power electronics.This work was supported by the U.K. Engineering and Physical Sciences Research Council for the University of Cambridge Centre for Doctoral Training under Grant EP/M506485/1 and by the French ANR Research Agency under grant ANR-16-CE05-0023 #Diamond-HVDC. The research leading to these results has been performed within the GREENDIAMOND project and received funding from the European Community's Horizon 2020 Programme (H2020/2014–2020) under grant agreement no. 640947

Diamond power devices: state of the art, modelling, figures of merit and future perspective

Abstract: With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22 W cm−1∙K−1 at RT of any material, high hole mobility (>2000 cm2 V−1 s−1), high critical electric field (>10 MV cm−1), and large band gap (5.47 eV), diamond has overwhelming advantages over silicon and other wide bandgap semiconductors (WBGs) for ultra-high-voltage and high-temperature (HT) applications (>3 kV and >450 K, respectively). However, despite their tremendous potential, fabricated devices based on this material have not yet delivered the expected high performance. The main reason behind this is the absence of shallow donor and acceptor species. The second reason is the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development. The third reason is that the best performances of diamond devices are expected only when the highest electric field in reverse bias can be achieved, something that has not been widely obtained yet. In this context, HT operation and unique device structures based on the two-dimensional hole gas (2DHG) formation represent two alternatives that could alleviate the issue of the incomplete ionization of dopant species. Nevertheless, ultra-HT operations and device parallelization could result in severe thermal management issues and affect the overall stability and long-term reliability. In addition, problems connected to the reproducibility and long-term stability of 2DHG-based devices still need to be resolved. This review paper aims at addressing these issues by providing the power device research community with a detailed set of physical models, device designs and challenges associated with all the aspects of the diamond power device value chain, from the definition of figures of merit, the material growth and processing conditions, to packaging solutions and targeted applications. Finally, the paper will conclude with suggestions on how to design power converters with diamond devices and will provide the roadmap of diamond device development for power electronics

Analytical Modeling of Nanoscale 4H-SiC MOSFETs for High Power Applications

Threshold voltage instability was investigated for 4H-SiC MOSFETs with SiO2, Si3N4 and HFO2 gate oxides. Threshold voltage changes observed in the drain current Vs. gate voltage (ID-VG) characteristics was determined using various gate voltage sweeps at room temperature. Three types of MOSFETs show different instability characteristics. Depending on gate voltage, many difficulties come up with 4H-SiC MOSFETs, such as low mobility and poor reliability. The characteristics like channel potential, field distribution and the threshold voltage of the proposed models of MOSFETs, 4H-SiC and SOI-4H-SiC were compared with simulator results to validate the models. Short channel effects (SCEs) were also investigated and compared with the existing nanoscale silicon MOSFETs The surface potential model is calculated by using the two-dimensional Poisson equation. The specification of the model are examined by several MOSFET parameters such as body doping concentration, metal gate work function, silicon carbide layer thickness, thickness of metal gate oxide layer, buried oxide thickness, drain to source voltage, and gate to source voltage. The outcomes of modeling and simulation of 4H-SiC MOSFETs model show that the proposed models can reduce short channel effects more than the Silicon MOSFETs. Proposed models highly reduces the drain-induced-barrier-lowering (DIBL) to meet the performance fullfilmant in Nano electronic applications when compared to silicon MOSFETs. Establishing the results, we have noticed that this model can be utilized as a useful tool for the characterization and design of high-efficiency 4H-SiC nanoscale MOSFETs. By matching the two-dimensional device simulation results with analytical modeling, the validity of the recommended models are proven

Advanced SiC/Oxide Interface Passivation

To save energy on an electric power grid, the idea of redesigned ‘micro-grids’ has been proposed. Implementation of this concept needs power devices that can operate at higher switching speeds and block voltages of up to 20 kV. Out of SiC and GaN wide band gap semiconductors, the former is more suitable for low- as well as high-voltage ranges. SiC exists in different polytypes 3C-, 4H- and 6H-. 4H-SiC due to its wider band gap, 3.26 eV has higher critical electric field of breakdown (Ec) and electron bulk mobility compared to 6H-SiC. Even with all these benefits 4H-SiC full potential has not yet been realized. This is due to high trap densities (Dit) at the interface. In addition to 4H-polytype, in recent years, there is a reignited interest on cubic silicon carbide (3C-SiC), which can be potentially grown heteroepitaxially on 12″ Si substrates, as it would result in a drastic cost reduction of semiconductor devices compared to the successful but exorbitantly expensive SiC hexagonal polytype technology (4H-SiC). In this chapter, we discuss and summarize all different interface passivation techniques or processes that have led to a vast improvement of these (4H- or 3C-SiC/SiO2) interfaces electrically

Characterisation of silicon carbide CMOS devices for high temperature applications

PhD ThesisIn recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.Engineering and Physical Sciences Research Council (EPSRC) and Raytheon U